Datasheet

Data Sheet AD8175
Rev. B | Page 5 of 40
TIMING CHARACTERISTICS (SERIAL MODE)
Specifications subject to change without notice.
Table 2.
Limit
Parameter Symbol Min Typ Max Unit
Serial Data Setup Time t
1
40 ns
CLK
Pulse Width t
2
60 ns
Serial Data Hold Time t
3
50 ns
CLK
Pulse Separation
t
4
140
ns
CLK
to
UPDATE
Delay t
5
10 ns
UPDATE
Pulse width t
6
90 ns
CLK
to SEROUT Valid t
7
120 ns
Propagation Delay,
UPDATE
to Switch On 80 ns
Data Load Time,
CLK
= 5 MHz, Serial Mode 9 µs
RST
Time 140 200 ns
LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE
t
2
t
4
1
0
CLK
1
0
SERIN
OUT8 (D4)
t
1
t
3
OUT8 (D3) OUT00 (D0)
1 = LATCHED
0 = TRANSPARENT
UPDATE
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURING LOW LEVEL
t
5
t
7
SEROUT
t
6
06478-002
Figure 2. Timing Diagram, Serial Mode
Table 3. Logic Levels, V
DD
= 3.3 V
V
IH
V
IL
V
OH
V
OL
I
IH
I
IL
I
OH
I
OL
SER
/PAR,
CLK
,
SERIN,
UPDATE
SER
/PAR,
CLK
,
SERIN,
UPDATE
SEROUT SEROUT
SER
/PAR,
CLK
,
SERIN,
UPDATE
SER
/PAR,
CLK
,
SERIN,
UPDATE
SEROUT SEROUT
2.0 V min 0.6 V max 2.8 V min 0.4 V max 20 µA max –20 µA max –1 mA min 1 mA min
Table 4. H and V Logic Levels, V
DD
= 3.3 V
V
OH
V
OL
I
OH
I
OL
2.7 V min 0.5 V max –3 mA max 3 mA max
Table 5.
RST
Logic Levels, V
DD
= 3.3 V
V
IH
V
IL
I
IH
I
IL
2.0 V min 0.6 V max −60 µA max −120 µA max
Table 6.
CS
Logic Levels, V
DD
= 3.3 V
V
OH
V
OL
I
IH
I
OL
2.0 V min 0.6 V max 100 µA max 40 µA max