Datasheet

Data Sheet AD8175
Rev. B | Page 17 of 40
TRUTH TABLE AND LOGIC DIAGRAM
Table 15. Operation Truth Table
WE
UPDATE
CLK
SERIN SEROUT
RST
SER
/PAR
CS
CMENC
Operation/Comment
X
X
X
X
X
0
X
X
X
Asynchronous reset. All
outputs are disabled. Contents
of 45-bit shift register are
unchanged.
0 1 1 X X 1 0 0 X Broadcast. The data on D0
through D4 is loaded into all
locations of the 45-bit shift
register. Data is not applied to
switch array.
1 1
SERIN
i
SERIN
i-45
1 0 0 X Serial mode. The data on the
SERIN line is loaded into the
45-bit shift register. The first bit
clocked into the shift register
appears at SEROUT 45 clock
cycles later. Data is not applied
to switch array.
0 1 1 X X 1 1 X X Parallel mode. The data on
parallel lines D0 through D4 is
loaded into the shift register
location addressed by A0
through A3. Data is not applied
to switch array. Chip select
feature is not applicable.
1 0 1 X X 1 X 0 X Switch array update. Data in
the 45-bit shift register is
transferred to the parallel
latches and applied to the
switch array.
1 X X X X 1 1 0 X No change in logic.