Datasheet

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500 MHz, Triple 16 × 9

Video Crosspoint Switch

Data Sheet

AD8175

Rev. B

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

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FEATURES

High channel count, triple 16 × 9 high speed, non-blocking

switch array

Differential or single-ended operation

Supports sync-on common-mode and sync-on color

operating modes

Decoded HV sync outputs available

G = +2 operation (differential input to differential output)

Flexible power supplies: +5 V or ±2.5 V

Logic ground for convenient control interface

Serial or parallel programming of switch array

High impedance output disable allows connection of

multiple devices with minimal loading on output bus

Adjustable output CM and black level through external pins

Excellent ac performance (to support 1600 × 1200 @ 85 Hz)

Bandwidth: 500 MHz

Slew rate: 1800 V/µs

Settling time: 4 ns to 1%

Low power of 3.5 W

Low all-hostile crosstalk

−88 dB @ 5 MHz

−46 dB @ 500 MHz

Wide input common-mode range of 4 V

Reset pin allows disabling of all outputs

Fully populated 26 x 26 ball PBGA package

(27 mm x 27 mm, 1 mm ball pitch)

Convenient grouping of RGB signals for easy routing

APPLICATIONS

RGB video switching

KVM

Professional video

FUNCTIONAL BLOCK DIAGRAM

INPUT

RECEIVER

G = +1

OUTPUT

BUFFER

G = +1

144

SET INDIVIDUAL, OR

RESET ALL OUTPUTS TO OFF

ENABLE/DISABLE

VBLK VOCM_CMENCON VOCM_CMENCOFF

16 x RGB

CHANNELS

CMENC

SERIN

RST

UPDATE

CLK

SER/PAR

D0 D1 D2 D3 D4 VPOS VNEG VDD DGND

SEROUT

9 x RGB, HV

CHANNELS

AD8175

06478-001

SWITCH

MATRIX

G = +2

45-BIT SHIFT

5-BIT PARALLEL

DECODE

9 × 5:16 DECODERS

PARALLEL LATCH

Figure 1.

GENERAL DESCRIPTION

The AD8175 is a high speed, triple 16 × 9 video crosspoint

switch matrix. It supports 1600 × 1200 RGB displays @ 85 Hz

refresh rate, by offering a 500 MHz bandwidth and a slew rate

of 1800 V/µs. With −88 dB of crosstalk and −94 dB isolation

(@ 5 MHz), the AD8175 is useful in many high speed video

applications.

The AD8175 supports two modes of operation: differential-in

to differential-out mode with sync-on CM signaling passed

through the switch and differential-in to differential-out mode

with CM signaling removed through the switch. The output

CM and black level can be conveniently set via external pins.

The independent output buffers of the AD8175 can be placed

into a high impedance state to create larger arrays by paralleling

crosspoint outputs. Inputs can be paralleled as well. The

AD8175 offers both serial and parallel programming modes.

The AD8175 is packaged in a fully-populated 26 × 26 ball

PBGA package and is available over the extended industrial

temperature range of −40°C to +85°C.

Summary of content (40 pages)

PAGE 1
Data Sheet 500 MHz, Triple 16 × 9 Video Crosspoint Switch AD8175 FEATURES FUNCTIONAL BLOCK DIAGRAM RGB video switching KVM Professional video DGND AD8175 A0 A1 A2 SERIN A3 SER/PAR WE 1 CLK 0 45-BIT SHIFT REGISTER WITH 5-BIT PARALLEL LOADING SEROUT UPDATE SET INDIVIDUAL, OR RESET ALL OUTPUTS TO OFF 45 CS PARALLEL LATCH RST CMENC 45 9 DECODE 9 × 5:16 DECODERS INPUT RECEIVER G = +1 R G B 144 OUTPUT BUFFER G = +1 2 2 2 2 2 2 R G B R G B 2 V 9 x RGB, HV CHANNELS SWITCH MATRIX
PAGE 2
AD8175 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions..............................8 Applications ....................................................................................... 1 Truth Table and Logic Diagram ............................................... 17 Functional Block Diagram ..............................................................
PAGE 3
Data Sheet AD8175 SPECIFICATIONS VS = ±2.5 V at TA = 25°C, G = +2, RL = 100 Ω (each output), VBLK = 0 V, output CM voltage = 0 V, differential I/O mode, unless otherwise noted. Table 1.
PAGE 4
AD8175 Parameter SWITCHING CHARACTERISTICS Enable On Time Switching Time, 2 V Step POWER SUPPLIES Supply Current Supply Voltage Range PSR OPERATING TEMPERATURE RANGE Temperature Range θJA Data Sheet Conditions Min Typ Max Unit 50% UPDATE to 50% output 50% UPDATE to 50% output 80 70 ns ns VPOS, outputs enabled, no load Outputs disabled VNEG, outputs enabled, no load Outputs disabled DVDD, outputs enabled, no load VPOS − VNEG VDD to DGND ΔVOUT, DM/ΔVPOS, ΔVPOS = ±0.5 V ΔVOUT, DM/ΔVNEG, ΔVNEG = ±0.
PAGE 5
Data Sheet AD8175 TIMING CHARACTERISTICS (SERIAL MODE) Specifications subject to change without notice. Table 2.
PAGE 6
AD8175 Data Sheet TIMING CHARACTERISTICS (PARALLEL MODE) Specifications subject to change without notice. Table 7.
PAGE 7
Data Sheet AD8175 ABSOLUTE MAXIMUM RATINGS POWER DISSIPATION Table 12.
PAGE 8
AD8175 Data Sheet A 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VNEG VNEG VNEG OPR7 ONB7 VNEG OPR8 ONB8 VPOS IPR8 INB8 VNEG IPR9 INB9 VPOS IPR10 INB10 VNEG IPR11 INB11 VPOS IPR12 INB12 VNEG VNEG VNEG A B B VNEG VNEG VNEG ONR7 OPB7 VNEG ONR8 OPB8 VPOS INR8 IPB8 VNEG INR9 IPB9 VPOS INR10 IPB10 VNEG INR11 IPB11 VPOS INR12 IPB12 VNEG VNEG VNEG C VNEG VNEG VNEG OPG7 ONG7 VNEG OPG8 ONG8 VPOS IPG8
PAGE 9
AD8175 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A VNEG VNEG VNEG INB12 IPR12 VPOS INB11 IPR11 VNEG INB10 IPR10 VPOS INB9 IPR9 VNEG INB8 IPR8 VPOS ONB8 OPR8 VNEG ONB7 OPR7 VNEG VNEG VNEG A B VNEG VNEG VNEG IPB12 INR12 VPOS IPB11 INR11 VNEG IPB10 INR10 VPOS IPB9 INR9 VNEG IPB8 INR8 VPOS OPB8 ONR8 VNEG OPB7 ONR7 VNEG VNEG VNEG B C VNEG VNEG VNEG ING12 IPG12 VPOS ING11 IPG11 VNEG ING10 IPG10
PAGE 10
AD8175 Data Sheet Table 14. Ball Grid Description Ball No.
PAGE 11
Data Sheet Ball No.
PAGE 12
AD8175 Ball No.
PAGE 13
Data Sheet Ball No.
PAGE 14
AD8175 Ball No.
PAGE 15
Data Sheet Ball No.
PAGE 16
AD8175 Ball No. AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 Mnemonic VNEG VNEG VNEG VNEG VNEG INR4 IPB4 VNEG INR3 IPB3 VPOS INR2 IPB2 VNEG INR1 IPB1 VPOS INR0 IPB0 VNEG ONR0 OPB0 VPOS ONR1 OPB1 VNEG VNEG Data Sheet Description Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Negative Analog Power Supply. Input Number 4, Negative Phase.
PAGE 17
Data Sheet AD8175 TRUTH TABLE AND LOGIC DIAGRAM Table 15. Operation Truth Table WE X UPDATE X CLK X SERIN X SEROUT X RST 0 SER/PAR X CS X CMENC X 0 1 1 X X 1 0 0 X 1 1 SERINi SERINi-45 1 0 0 X 0 1 1 X X 1 1 X X 1 0 1 X X 1 X 0 X 1 X X X X 1 1 0 X Rev. B | Page 17 of 40 Operation/Comment Asynchronous reset. All outputs are disabled. Contents of 45-bit shift register are unchanged. Broadcast.
PAGE 18
A0 A1 A2 A3 OUTPUT ADDRESS 4 TO 9 DECODER CS CLK WE SERIN Figure 7. Logic Diagram Rev.
PAGE 19
Data Sheet AD8175 EQUIVALENT CIRCUITS VPOS 10kΩ 0.1pF OPn, ONn VBLK, VOCM_CMENCOFF 10kΩ 0.1pF 1kΩ 06478-012 06478-007 1kΩ (VPOS – VNEG) 2 VNEG Figure 13. VBLK and VOCM_CMENCOFF Inputs (see also ESD Protection Map, Figure 19) Figure 8. Enabled Output (see also ESD Protection Map , Figure 19) VPOS VPOS 20kΩ OPn 20kΩ VNEG 3.1kΩ 0.4pF 3.33kΩ 0.3pF 3.4pF VOCM_CMENCON VPOS 3.4pF 3.33kΩ 0.3pF 20kΩ 06478-008 VNEG VNEG Figure 9.
PAGE 20
Data Sheet VDD VDD VNEG DGND IPn, INn, OPn, ONn, VBLK, VOCM_CMENCOFF VOCM_CMENCON 06478-016 SEROUT, H, V DGND VPOS Figure 19. ESD Protection Map Figure 18. SEROUT, H, V Logic Outputs (see also ESD Protection Map, Figure 19) Rev.
PAGE 21
Data Sheet AD8175 TYPICAL PERFORMANCE CHARACTERISTICS VS = ±2.5 V at TA = 25°C, G = +2, RL = 100 Ω (each output), VBLK = 0 V, output CM voltage = 0 V, differential I/O mode, unless otherwise noted. 12 0.15 10 0.10 8 0.05 VOUT, DIFF (V) GAIN (dB) 6 4 2 0 –0.05 0 –2 –0.10 1 10 100 1000 FREQUENCY (MHz) –0.15 06478-031 –6 2 4 6 8 10 12 14 16 18 20 TIME (ns) 06478-033 –4 Figure 23. Small Signal Pulse Response, 200 mV p-p Figure 20.
PAGE 22
AD8175 Data Sheet 5 0 4 –20 2 CROSSTALK (dB) OUTPUT ERROR (%) 3 1 0 –1 –2 –3 –40 –60 –80 –100 2 3 4 5 6 7 8 9 10 TIME (ns) –120 1 0 4000 –1 3000 –20 1850V/µs PEAK –2 2000 –3 1000 –4 0 –5 3 4 5 6 7 8 9 FEEDTHROUGH (dB) 5000 SLEW RATE (V/µs) 1 0 –40 –60 –80 –100 –1000 10 TIME (ns) –120 06478-046 VOUT, DIFF (V) 6000 2 1000 Figure 29. Crosstalk, All Hostile 2 1 100 FREQUENCY (MHz) Figure 26.
PAGE 23
Data Sheet AD8175 10000 600 |Ipos| AND |Ineg| (BROADCAST) |Ipos| AND |Ineg| (mA) 500 IMPEDANCE (Ω) 400 300 |Ipos| AND |Ineg| (ALL OUTPUTS DISABLED) 200 1000 100 10 100 1000 06478-051 1 1000 06478-052 TEMPERATURE (°C) 100 1000 06478-039 10 20 30 40 50 60 70 80 90 100 06478-043 0 –50 –40 –30 –20 –10 0 FREQUENCY (MHz) Figure 32. Quiescent Supply Currents vs. Temperature Figure 35.
PAGE 24
AD8175 Data Sheet 1.0 20 2500 2250 RED 15 2000 GREEN BLUE 1750 10 –0.5 5 HSYNC 1500 COUNT 0 VOUT (V) VOUT, COMMON MODE (V) 0.5 1000 750 VSYNC –1.0 1250 0 500 100 200 300 400 500 600 700 800 900 0 06478-058 0 –5 1000 TIME (ns) –70 –60 –50 –40 –30 –20 –10 0 Figure 38. Common-Mode Pulse Response Figure 41. VOS Distribution 0 2.0 –10 1.5 1.0 31µV/°C –30 0.5 VOS (mV) –40 –50 –0.5 –60 –1.0 –70 10 100 1000 FREQUENCY (MHz) –2.
PAGE 25
Data Sheet AD8175 6 0.025 1.2 VOUT UPDATE 5 0.020 1.0 0.6 2 0.4 1 0.2 0 0 NORMALIZED DC GAIN (dB) 3 VOUT, SINGLE-ENDED (V) 0.8 0.010 0.005 0 40ppm/°C –0.005 –0.010 –0.015 0 20 40 60 –0.2 80 100 120 140 160 180 200 220 240 260 280 TIME (ns) Figure 44. Enable Time –0.025 –40 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 45. Normalized DC Gain vs. Temperature Rev. B | Page 25 of 40 100 06478-054 –0.020 –1 06478-042 UPDATE (V) 0.
PAGE 26
AD8175 Data Sheet THEORY OF OPERATION The AD8175 is a non-blocking crosspoint with 16 differential RGB input channels and nine differential RGB output channels. Although the AD8175 is primarily meant for differential-in, differential-out middle-of-CAT5-run applications, each differential RGB output channel is complemented by H and V syncs for use in end-of-CAT5-run, single-ended output applications.
PAGE 27
Data Sheet AD8175 APPLICATIONS OPERATING MODES Depending on the state of the CMENC logic input, the AD8175 can be set in either of two differential-in, differential-out operating modes. An additional application is possible by tapping the outputs single-ended and making use of the decoded H and V outputs. VOCM_CMENCOFF and VBLK both set to 0 V. (Note that both pulses have been slightly shifted off the 0 V line for clarity.) VOCM_CMENCOFF = 0V 0.
PAGE 28
AD8175 Data Sheet PROGRAMMING DIFF. R DIFF. B CMR DIFF. R CMB DIFF. B CMR INPUT OVERALL CM CMB AD8175 OUTPUT OVERALL CM DIFF. G CMG DIFF. G 06478-022 CMG CMENC VOCM_CMENCON Figure 49. AD8175 in Middle-of-CAT5-Run Application, CM Encoding On (Note that in this application, the H and V outputs, though asserted, are not used) In this operation mode, the difference Δdiff = VBLK − VOCM_CMENCOFF still adds an output differential voltage, as described in the previous section.
PAGE 29
Data Sheet AD8175 If more than one AD8175 device is to be serially programmed in a system, the SEROUT signal from one device can be connected to the SERIN of the next device to form a serial chain. All of the CLK, UPDATE, and SER/PAR pins should be connected in parallel and operated as described above. The serial data is input to the SERIN pin of the first device of the chain, and it will ripple through to the last.
PAGE 30
AD8175 Data Sheet difference is that the SER/PAR pin is held low, as if serial programming were taking place. By holding CLK high, no serial clocking will occur, and instead, the WE can be used to clock all first rank latches in the chip at once. DIFFERENTIAL AND SINGLE-ENDED OPERATION Although the AD8175 has fully differential inputs and outputs, it can also be operated in a single-ended fashion.
PAGE 31
Data Sheet AD8175 signal-frequency current flows at the undriven input, such input should be treated as a signal line in the board design. For example, in order to achieve best dynamic performance, the undriven input should be terminated with an impedance matching that seen by the part at the driven input. Differential Output Benefits of Differential Operation The AD8175 has a fully-differential switch core with differential outputs.
PAGE 32
AD8175 Data Sheet input terminals. One output increases in voltage, while the other decreases an equal amount to make the total output voltage difference correct. The average of these output voltages is forced to the voltage on the common-mode reference terminal (VOCM_CMENCOFF or VOCM_CMENCON) by a second control loop. If only one output terminal is observed with respect to the common-mode reference terminal, only half of the difference voltage will be observed.
PAGE 33
Data Sheet AD8175 VPOS Power Dissipation Calculation of Power Dissipation IO, QUIESCENT 10 QNPN TJ = 150°C VOUTPUT 9 IOUTPUT IO, QUIESCENT 7 06478-025 MAXIMUM POWER (W) QPNP 8 VNEG 6 Figure 52. Simplified Output Stage 5 Example For the AD8175, with an ambient temperature of 85°C, all nine RGB output channels driving 1 Vrms into 100 Ω loads, and power supplies at ±2.5 V, follow these steps: 3 15 25 35 45 55 65 75 AMBIENT TEMPERATURE (°C) 85 06478-036 4 1. Figure 51.
PAGE 34
AD8175 Data Sheet In a general case, the power delivered by the digital supply and dissipated into the digital output devices has to be taken into account following a similar derivation. However, since the loads driven by the H and V outputs is high and since the voltage at these outputs typically sits close to either rail, the correction to the on-chip power estimate is small. Furthermore, the H and V outputs are active only briefly during sync generation and returned to digital ground thereafter.
PAGE 35
Data Sheet AD8175 example, input channel INPUT0. INPUT0 is programmed to connect to one of the AD8175 outputs where the measurement can be made. First, the crosstalk terms associated with driving a test signal into each of the other 15 input channels can be measured one at a time, while applying no signal to INPUT0.
PAGE 36
AD8175 Data Sheet driven from a 75 Ω terminated cable, the input crosstalk can be reduced by buffering this signal with a low output impedance buffer. On the output side, the crosstalk can be reduced by driving a lighter load. Although the AD8175 is specified with excellent settling time when driving a properly terminated CAT5, the crosstalk is higher than the minimum obtainable due to the high output currents.
PAGE 37
Data Sheet AD8175 AD8175 IPn OPn INn 50Ω 06478-026 ONn Figure 53. Fly-By Input Termination (Grounds for the two transmission lines shown must be tied together close to the INn pin) If multiple AD8175s are to be driven in parallel, a fly-by input termination scheme is very useful, but the distance from each AD8175 input to the driven input transmission line is a stub that should be minimized in length and parasitics using the discussed guidelines.
PAGE 38
AD8175 Data Sheet VPOS FOUR 15-PIN HD CONNECTORS VDD FOUR AD8147 (G = +2) AD8003 (G = +4) 15-PIN HD CONNECTOR PC THREE 15-PIN HD CONNECTORS THREE RGB, HV CHANNELS FOUR RGB, HV CHANNELS OUT0 TO OUT2 IN0 TO IN3 FOUR 15-PIN HD CONNECTORS FOUR AD8147 (G = +2) FOUR DIFFERENTIAL RGB WITH SYNC-ON CM CHANNELS THREE 15-PIN HD CONNECTORS THREE RGB, HV CHANNELS THREE RGB CHANNELS OUT3 TO OUT5 RGB MONITOR RGB MONITOR 15-PIN HD CONNECTOR PC FOUR RGB, HV CHANNELS THREE HV PAIRS IN0 TO IN3 IN4 TO I
PAGE 39
Data Sheet AD8175 OUTLINE DIMENSIONS 27.20 27.00 SQ 26.80 A1 CORNER INDEX AREA 26 25 24 6 22 20 18 16 14 12 10 8 4 2 23 21 19 17 15 13 11 9 3 5 7 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF A1 BALL PAD CORNER 24.20 24.00 SQ 23.80 25.00 BSC SQ TOP VIEW 1.00 BSC 1.00 REF DETAIL A 1.22 1.17 1.12 DETAIL A 0.66 0.61 0.56 0.50 NOM 0.40 MIN 0.70 0.60 0.50 BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MS-034-AAL-1 COPLANARITY 0.20 MAX SEATING PLANE 051208-C 2.45 2.28 2.08 Figure 55.