Datasheet

AD8158
Rev. B | Page 9 of 36
Pin No. Mnemonic Type Description
95 SEL3 Control
1
Lane 3 A/B Switch Control
96 SEL2 Control
1
Lane 2 A/B Switch Control
97 SEL1 Control
1
Lane 1 A/B Switch Control
98 SEL0 Control
1
Lane 0 A/B Switch Control
99 BICAST Control
1
Enable Bicast Mode for Port A and Port B Outputs, Active
High
100 SEL4G Control
1
Set Transmitter for Low Speed PE, Active High
1
Logic level of control pins referred to DV
CC
.
2
EQ control pins (EQ_A[1:0], EQ_B[1:0], EQ_C[1:0]) require 5 kΩ in series when DV
CC
> V
CC
.