Datasheet

AD8158
Rev. B | Page 5 of 36
I
2
C TIMING SPECIFICATIONS
SCL
S Sr
NOTES
1. S = START CONDITION.
2. Sr = REPEAT START.
3. P = STOP.
SP
SD
A
t
F
t
LOW
t
HD;STA
t
HD;DAT
t
SU;DAT
t
SU;STA
t
HD;STA
t
HIGH
t
R
t
F
t
SU;STO
t
R
t
BUF
06646-102
Figure 2. I
2
C Timing Diagram
Table 2. I
2
C Timing Parameters
Parameter Symbol Min Max Unit
SCL Clock Frequency f
SCL
0 400+ kHz
Hold Time for a Start Condition t
HD;STA
0.6 μs
Setup Time for a Repeated Start Condition t
SU;STA
0.6 μs
Low Period of the SCL Clock t
LOW
1.3 μs
High Period of the SCL Clock t
HIGH
0.6 μs
Data Hold Time t
HD;DAT
0 μs
Data Setup Time t
SU;DAT
10 ns
Rise Time for Both SDA and SCL t
R
1 300 ns
Fall Time for Both SDA and SCL t
F
1 300 ns
Setup Time for Stop Condition t
SU;STO
0.6 μs
Bus Free Time Between a Stop and a Start Condition t
BUF
1 μs
Bus Free Time After a Reset 1 μs
Reset Pulse Width
1
10 ns
1
Reset pulse width is defined as the time RESETB is held below the logic low threshold (V
IL
) listed in Table 1 while the DV
CC
supply is within the operating range in Table 1.