Datasheet

AD8158
Rev. B | Page 35 of 36
Mnemonic Addr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default
RXC Disable 0xC0 RXDIS C3 RXDIS C2 RXDIS C1 RXDIS C0 0x00
RXC Setting 0xC1 CEQ[3] CEQ[2] CEQ[1] CEQ[0] 0x00
RXC LOS Ctrl 0xD1 Set to 0 Set to 0 Set to 0 Set to 0 Set to 0 LOS_FILT Set to 0 LOS_ENB 0x05
RXC Lane 1/
RXC Lane 0
Setting
0xC2
1
C1EQ[3] C1EQ[2] C1EQ[1] C1EQ[0] C0EQ[3] C0EQ[2] C0EQ[1] C0EQ[0] 0x00
RXC Lane 3/
RXC Lane 2
Setting
0xC3
1
C3EQ[3] C3EQ[2] C3EQ[1] C3EQ[0] C2EQ[3] C2EQ[2] C2EQ[1] C2EQ[0] 0x00
RXC P/N
Swap
0xC4
1
PNC3 PNC2 PNC1 PNC0 0x00
RXC LOS
Status
0xC5
1
LOSC3
Sticky
LOSC2
Sticky
LOSC1
Sticky
LOSC0
Sticky
LOSC3 Active LOSC2
Active
LOSC1
Active
LOSC0
Active
TXC Disable 0xC8 TXDIS C3 TXDIS C2 TXDIS C1 TXDIS C0 0x00
TXC Level/PE
Control
0xC9 CLEV[1] CLEV[0] CPE[2] CPE[1] CPE[0] 0x20
TXC Lane1/
TXC Lane 0
PE Setting
0xCA
1
C1PE[2] C1PE[1] C1PE[0] C0PE[2] C0PE[1] C0PE[0] 0x00
TXC Lane2/
TXC Lane 3
PE Setting
0xCB
1
C3PE[2] C3PE[1] C3PE[0] C2PE[2] C2PE[1] C2PE[0] 0x00
TXC Per-Lane
Level Setting
0xCC
1
C3OLEV[1] C3OLEV[0] C2OLEV[1] C2OLEV[0] C1OLEV[1] C1OLEV[0] C0OLEV[1] C0OLEV[0] 0xAA
1
Per-lane registers.