Datasheet

AD8158
Rev. B | Page 31 of 36
SUPPLY SEQUENCING
Ideally, all power supplies should be brought up to the appropri-
ate levels simultaneously (power supply requirements are set by
the supply limits in Table 1 and the absolute maximum ratings
listed in Table 3). In the event that the power supplies to the
AD8158 are brought up separately, the supply power-up sequence
is as follows: DV
CC
is powered first, followed by V
CC
, and lastly
V
TTI
and V
TTO
. The power-down sequence is reversed, with V
TTI
and V
TTO
being powered off first.
V
TTI
and V
TTO
contain ESD protection diodes to the V
CC
power
domain (see Figure 38 and Figure 39). To avoid a sustained high
current condition in these devices (I
SUSTAINED
< 64 mA), the V
TTI
and V
TTO
supplies should be powered on after V
CC
and should
be powered off before V
CC
.
If the system power supplies have a high impedance in the
powered off state, then supply sequencing is not required
provided the following limits are observed:
• Peak current from V
TTI
or V
TTO
to V
CC
< 200 mA
• Sustained current from V
TTI
or V
TTO
to V
CC
< 64 mA
RESET
On initial power up or at any point during operation the
AD8158 register set can be restored to the default values by
pulling the RESETB pin low. Reset pulse width is defined as the
time RESETB is held below the logic low threshold (V
IL
) listed
in Table 1 while the DV
CC
supply is within the operating range
in Table 1. During normal operation the RESETB pin must be
pulled up to DV
CC
. A software reset is available by writing value
0x01 to the Reset register at address 0x00. This register
is write only.
SINGLE SUPPLY vs. MULTIPLE SUPPLY
OPERATION
The AD8158 supports a flexible supply voltage of 1.8 V to 3.3 V.
For some dc-coupled links, 1.2 V or ground-referenced signaling
may be desired. In these cases, the AD8158 can be run with a
split supply configuration. An example is shown in Figure 47.
TX
RX
0
V
V
TTO
V
CC
DV
CC
50Ω 50Ω 50Ω50Ω
V
TTI
CML
AD8158
Z
0
Z
0
V
EE
= –3.3V (OR –1.8V)
V
OH
= 0mV
V
OL
= –400mV
Z
0
Z
0
+
–
MCU
MCU_V
DD
MCU_V
SS
DV
CC
TO AD8158
I
2
C_SCL
I
2
C_SDA
V
EE
ADuM1250
06646-148
Figure 47. Multiple Supply Operation
Table 21. Alternate Supply Configuration Examples
Signal Level V
CC
, V
TTI
, V
TTO
V
EE
1.2 V CML 1.2 V −2.1 V ≤V
EE
≤ −0.6 V
GND − 400 mV diff GND −3.3 V ≤V
EE
≤ −1.8 V
The AD8158 control signals are always referenced between
DV
CC
and V
EE
and, when using a split supply configuration,
logic level-shift circuits should be used. The evaluation board
design shows the use of the Analog Devices, Inc., ADUM1250
I
2
C isolator and a level shifter to level-shift the SCL and SDA
signals (for information about the evaluation board, see the
Ordering Guide).
Evaluation of DC-Coupled Links
When evaluating the AD8158 dc-coupled, note that most lab
equipment is ground referenced whereas the AD8158 high
speed I/O are connected by 50 Ω on-die termination resistors to
V
TTI
and V
TTO
. To interface the AD8158 to ground-referenced,
high speed instrumentation (for example, the 50 Ω inputs of a
high speed oscilloscope), it is necessary to level-shift the outputs by
either using a dc-blocking network or powering the AD8158
between ground and a negative supply.
For example, to evaluate 1.8 V dc-coupled transmitter perfor-
mance with a 50 Ω ground-referenced oscilloscope, use the
following supply configuration:
V
CC
= V
TTO
= V
TTI
= Ground
V
EE
= −1.8 V
Ground < DVCC < 1.5 V