Datasheet

AD8158
Rev. B | Page 19 of 36
RECEIVERS
The AD8158 receivers incorporate 50 Ω on-chip termination,
ESD protection, and a multizero equalization function capable
of delivering up to 18 dB of boost at 4.25 GHz. The AD8158 can
compensate signal degradation at 6.5 Gbps from over 40 inches
of FR4 backplane trace. The receive path also incorporates a
loss-of-signal (LOS) function that squelches the associated
transmitter when the midband differential voltage falls below a
specified threshold value. Finally, the receivers implement a sign-
swapping option (P/N swap), which allows the user to invert the
sign of the input signal path and eliminates the need for board-
level crossovers in the receive channels.
Input Structure and Allowed Input Levels
The AD8158 tolerates an input common-mode range (meas-
ured with zero differential input) of
V
EE
+ 0.6 V < V
ICM
< V
CC
+ 0.3 V
Typical supply configurations include, but are not limited to,
those listed in Table 9.
Table 9. Typical Input Supply Configurations
Configuration DV
CC
V
CC
V
TTI
Low V
TTI
, AC-Coupled Input 3.3 V − 1.8 V 1.8 V 1.6 V
Single 1.8 V Supply 3.3 V − 1.8 V 1.8 V 1.8 V
3.3 V Core 3.3 V 3.3 V 1.8 V
Single 3.3 V Supply 3.3 V 3.3 V 3.3 V
When dc-coupling with LVDS, CML, or ECL signals, it can
be advantageous to operate with split or negative supplies
(see the Applications Information section). In these appli-
cations, it is necessary to observe the maximum voltage ratings
between V
CC
and V
EE
and to select supply voltages for V
TTO
and
V
TTI
in the range of V
CC
to V
EE
to avoid activating the ESD
protection devices.
RP
52Ω
RN
52Ω
R1
750Ω
R2
750Ω
R3
1kΩ
RLP
RL
Q1
Q2
I1
RLN
RL
V
CC
V
TTI
IP_xx
IN_xx
V
EE
06646-138
Figure 37. Simplified Receiver Input Structure
Equalizer Settings
Every input lane offers a low power, asynchronous, programma-
ble receive equalizer for NRZ data up to 6.5 Gbps. The pin control
interface allows two levels of receive equalization. Register-based
control allows the user 10 equalizer settings. Register and pin
control boost settings are listed in Table 10. Equalization capa-
bility and resulting jitter performance are illustrated in Figure 30,
Figure 31, and Figure 34. Figure 34 shows the loss characteristic
of various reference channels, and Figure 30 and Figure 31 show
resulting DJ and RJ performance vs. equalizer setting against these
channels.
The four LSBs of Register 0x41, Register 0x81, and Register 0xC1
allow programming of all the equalizers in a port simultane-
ously (see Table 13). The 0x42, 0x82, and 0xC2 registers allow
per-lane programming of the equalizers (see Table 22). Be
aware that writing to the port-level equalizer registers updates
and overwrites per-lane settings.
Table 10. Equalizer Settings
Equalization
Boost (dB) EQ Register Setting EQ[1:0] Pins
0 0 00
2 1 N/A
4 2 01
6 3 N/A
8 4 10
10 5 N/A
12 6 N/A
14 7 N/A
16 8 N/A
18 9 11
RP
R
TERM
RN
R
TERM
ON-CHIP TERMINATIONESD
EQUALIZER
LOSS
OF
SIGNAL
DETECT
V
THRESH
SIG
EQ OUT
V
CC
V
TTI
IP_xx
IN_xx
V
EE
06646-137
Figure 38. Functional Diagram of the AD8158 Receiver