Datasheet

AD8158
Rev. B | Page 11 of 36
50Ω CABLES
2 2
TP3
HIGH
SPEED
SAMPLING
OSCILLOSCOPE
50Ω CABLES
2 2
50Ω
AD8158
AC-COUPLED
EVALUATION
BOARD
INPUT
PIN
OUTPUT
PIN
PATTERN
GENERATOR
DATA OUT
TP1
50Ω CABLES
2 2
TP2
FR4 TEST BACKPLANE
DIFFERENTIAL
STRIPLINE TRACES
8mils WIDE, 8mils SPACE,
8mils DIELECTRIC HEIGHT
TRACE LENGTHS = 20 INCHES,
40 INCHES
25ps/DIV
200mV/DI
V
REFERENCE EYE DIAGRAM AT TP1
06646-007
Figure 7. Input Equalization Test Circuit
25ps/DIV
200mV/DI
V
06646-008
Figure 8. 6.5 Gbps Input Eye, 20 Inch FR4 Input Channel (TP2 from Figure 7)
25ps/DIV
200mV/DI
V
06646-009
Figure 9. 6.5 Gbps Input Eye, 40 Inch FR4 Input Channel (TP2 from Figure 7)
25ps/DIV
200mV/DI
V
06646-010
Figure 10. 6.5 Gbps Output Eye, 20 Inch FR4 Input Channel (TP3 from Figure 7)
25ps/DIV
200mV/DI
V
06646-011
Figure 11. 6.5 Gbps Output Eye, 40 Inch FR4 Input Channel (TP3 from Figure 7)