Datasheet

6.5 Gbps
Quad Buffer Mux/Demux
AD8158
Rev. B
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FEATURES
Quad 2:1 mux/1:2 demux
Optimized for dc to 6.5 Gbps NRZ data
Per-lane P/N pair inversion for routing ease
Programmable input equalization
Compensates up to 40 inches of FR4
Loss-of-signal detection
Programmable output pre-emphasis up to 12 dB
Programmable output levels with squelch and disable
Accepts ac-coupled or dc-coupled differential CML inputs
50 Ω on-chip termination
1:2 demux supports unicast or bicast operation
Port-level loopback
Port or single lane switching
1.8 V to 3.3 V flexible core supply
User-settable I/O supply from V
CC
to 1.2 V
Low power, typically 2.0 W in basic configuration
100-lead LFCSP
−40°C to +85°C operating temperature range
APPLICATIONS
Low cost redundancy switch
SONET OC48/SDH16 and lower data rates
XAUI/GbE/FC/Infiniband over backplane
OIF CEI 6.25 Gbps over backplane
Serial data-level shift
4-/8-/12-lane equalizers or redrivers
FUNCTIONAL BLOCK DIAGRAM
O
x_B[3:0]
TRANSMIT
PRE-
EMPHASIS
QUAD
2:1
MULTIPLEXER/
1:2
DEMULTIPLEXER
RECEIVE
EQUALIZATION
TRANSMIT
PRE-
EMPHASIS
Ox_C[3:0]
Ix_C[3:0]
O
x_A[3:0]
TOGGLE
CONTROL
LOGIC
LB_A
LB_B
LB_C
PE_A
PE_B
PE_C
EQ_A[1:0]
EQ_B[1:0]
EQ_C[1:0]
SEL[3:0]
BICAST
SEL4G
RESETb
LOS_INT
2:1
1:2
RECEIVE
EQUALIZATION
Ix_A[3:0]
EQ
Ix_B[3:0]
I
2
C
CONTROL
LOGIC
SCL
SDA
I2C_A0
I2C_A1
I2C_A2
EQ
EQ
AD8158
06646-001
Figure 1.
GENERAL DESCRIPTION
The AD8158 is an asynchronous, protocol-agnostic, quad-lane
2:1 switch with a total of 12 differential CML inputs and
12 differential CML outputs. The signal path supports NRZ
signaling with data rates up to 6.5 Gbps per lane. Each lane
offers programmable receive equalization, programmable
output pre-emphasis, programmable output levels, and loss-of-
signal detection.
The nonblocking switch-core of the AD8158 implements a
2:1 multiplexer and 1:2 demultiplexer per lane and supports
independent lane switching through the four select pins,
SEL[3:0]. Each port is a four-lane link. Every lane implements
an asynchronous path supporting dc to 6.5 Gbps NRZ data,
fully independent of other lanes. The AD8158 has low latency
and very low lane-to-lane skew.
The main application of the AD8158 is to support redundancy
on both the backplane and the line interface sides of a serial
link. The demultiplexing path implements unicast and bicast
capability, allowing the part to support either 1 + 1 or 1:1
redundancy.
The AD8158 is also suited for testing high speed serial links
because of its ability to duplicate incoming data. In a port-
monitoring application, the AD8158 can maintain link-
connectivity with a pass-through connection from Port C to
Port A while sending a duplicate copy of the data to test
equipment on Port B.
The rich feature set of the AD8158 can be controlled either
through external toggle pins or by setting on-chip control
registers through the I
2
C interface.

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