Datasheet

AD8156
Rev. 0 | Page 6 of 20
CS
UPD
WE
OUTxN/P
ENABLE
OUTxN/P
DISABLE
OUTxN/P
TOGGLE
t
WOE
t
WOD
t
WOT
t
WHU
06305-004
Figure 4. Transparent Write and Update Cycle
DATA[3:0]
ADDR[3:0]
ADDR1 ADDR2
DATA2DATA1
RE
CS
t
CSR
t
RDE
t
AA
t
RHA
t
CHR
t
RDD
06305-005
Figure 5. Second Rank Readback Cycle
t
TOD
t
TW
OUTxN/P
DISABLE
RST
06305-006
Figure 6. Asynchronous Reset