AD8156
Rev. 0 | Page 5 of 20
TIMING DIAGRAMS
D[3:0]
[3:0]
WE
CS
t
CSW
t
ASW
t
WP
t
DSW
t
DHW
t
AHW
t
CHW
06305-002
Figure 2. First Rank Write Cycle
CS
UPD
OUTxN/P
ENABLE
OUTxN/P
DISABLE
OUTxN/P
TOGGLE
t
UOD
t
UOT
t
UOE
t
CSU
t
UW
t
CHU
06305-003
Figure 3. Second Rank Update Cycle
