Datasheet

AD8153
Rev. 0 | Page 8 of 24
50Ω CABLES
2 2
TP3
HIGH-
SPEED
SAMPLING
OSCILLOSCOPE
50Ω CABLES
2 2
50Ω
AD8153
AC COUPLED
EVALUATION
BOARD
INPUT
PIN
OUTPUT
PIN
PATTERN
GENERATOR
DATA OUT
TP1
50Ω CABLES
2 2
TP2
FR4 TEST BACKPLANE
DIFFERENTIAL
STRIPLINE TRACES
8mils WIDE, 8mils SPACE,
8mils DIELECTRIC HEIGHT
TRACE LENGTHS = 20 INCHES,
40 INCHES
06393-015
40ps/DIV
150mV/DI
V
REFERENCE EYE DIAGRAM AT TP1
Figure 7. Input Equalization Test Circuit
40ps/DIV
150mV/DI
V
06393-024
Figure 8. 3.2 Gbps Input Eye, 20 Inch FR4 Input Channel
(TP2 from
Figure 7)
40ps/DIV
150mV/DI
V
06393-025
Figure 9. 3.2 Gbps Input Eye, 40 Inch FR4 Input Channel
(TP2 from
Figure 7)
40ps/DIV
150mV/DI
V
06393-026
Figure 10. 3.2 Gbps Output Eye, 20 Inch FR4 Input Channel, High EQ
(TP3 from
Figure 7)
40ps/DIV
150mV/DI
V
06393-027
Figure 11. 3.2 Gbps Output Eye, 40 Inch FR4 Input Channel, High EQ
(TP3 from
Figure 7)