Datasheet

AD8153
Rev. 0 | Page 4 of 24
I
2
C TIMING SPECIFICATIONS
SDA
SCL
t
f
t
LOW
t
HD;STA
t
r
t
HD;DAT
t
HIGH
t
SU;DAT
t
f
t
SU;STA
t
HD;STA
t
SP
t
SU;STO
t
r
t
BUF
SPSrS
06393-006
Figure 2. I
2
C Timing Diagram
Table 2.
Parameter Symbol Min Max Unit
SCL Clock Frequency f
SCL
0 400+ kHz
Hold Time for a Start Condition t
HD;STA
0.6 – μs
Set-up Time for a Repeated Start Condition t
SU;STA
0.6 – μs
Low Period of the SCL Clock t
LOW
1.3 – μs
High Period of the SCL Clock t
HIGH
0.6 – μs
Data Hold Time t
HD;DAT
0 – μs
Data Set-Up Time t
SU;DAT
10 – ns
Rise Time for Both SDA and SCL t
r
1 300 ns
Fall Time for Both SDA and SCL t
f
1 300 ns
Set-Up Time for Stop Condition t
SU;STO
0.6 – μs
Bus Free Time Between a Stop Condition and a Start Condition t
BUF
1 – ns
Capacitance for Each I/O Pin C
i
5 7 pF