Datasheet

REV. A
AD8152
–15–
CS
UPDATE
INPUT {DATA 1}
WE
ENABLING
OUT[0:33][N:P]
OUTPUTS
DISABLING
OUT[0:33][N:P]
OUTPUTS
INPUT {DATA 1}INPUT {DATA 0}
t
CSU
t
UOT
t
UOE
t
UW
t
WOT
t
WOD
t
WHU
t
CHU
INPUT {DATA 2}
Figure 4a. Transparent Write and Update Cycle
Table VII. Transparent Update Cycle
Symbol Parameter Conditions Min Typ Max Unit
t
CSU
Setup Time Chip Select to Update T
A
= 25ⴗC0 ns
t
CHU
Hold Time Chip Select from Update VCC = 3.3 V 0 ns
t
UOE
Output Enable Times Update to Output Enable 35 50 ns
t
WOE
* Write Enable to Output Enable 35 50 ns
t
UOT
Output Toggle Times Update to Output Reprogram 25 45 ns
t
WOT
Write Enable to Output Reprogram 25 45 ns
t
UOD
* Output Disable Times Update to Output Disabled 25 45 ns
t
WOD
Write Enable to Output Disabled 25 45 ns
t
WHU
Setup Time Write Enable to Update 0 ns
t
UW
Width of Update Pulse 10 ns
*Not shown
CS
RE
INPUT
D[5:0]
A[5:0]
OUTPUTS
ADDR 1 ADDR 2
{ADDR 1}
DATA
DATA {ADDR 2}
t
AA
t
RDE
t
CSR
t
RHA
t
CHR
t
RDD
Figure 4b. Second Rank Readback Cycle
Table VIII. Second Rank Readback Cycle
Symbol Parameter Conditions Min Typ Max Unit
t
CSR
Setup Time Chip Select to Read Enable T
A
= 25ⴗC0 ns
t
CHR
Hold Time Chip Select from Read Enable VCC = 3.3 V 0 ns
t
RHA
Address from Read Enable 5 ns
t
RDE
Enable Time Data from Read Enable 15 ns
t
AA
Access Time Data from Address 15 30 ns