Datasheet

AD8151
Rev. B | Page 20 of 40
To ensure proper operation, all outputs (including unused
output) must be pulled high using external pull-up networks to
a level within the output compliance range. If outputs from
multiple AD8151s are wired together, a single pull-up network
can be used for each output bus. The pull-up network should be
chosen to keep the output voltage levels within the output
compliance range at all times. Recommended pull-up networks
to produce PECL/ECL 100 kΩ and 10 kΩ compatible outputs
are shown in
Figure 36. Alternatively, a separate supply can be
used to provide V
COM
, making R
COM
and D
COM
unnecessary.
02169-036
OUTyyN
OUTyyP
AD8151
OUTyyN
OUTyyP
AD8151
V
CC
R
L
R
L
R
L
V
CC
R
L
V
COM
R
COM
V
COM
D
COM
Figure 36. Output Pull-Up Networks for PECL/ECL: a) 100 kΩ and b) 10kΩ
The output levels are
V
OH
= V
COM
V
OL
= V
COM
– I
OUT
R
L
V
SWING
= V
OH
− V
OL
= I
OUT
R
L
V
COM
= V
CC
– I
OUT
R
COM
(100 kΩ mode)
V
COM
= V
CC
– V(D
COM
) (10 kΩ mode)
The common-mode adjustment element (R
COM
or D
COM
) can be
omitted if the input range of the receiver includes the positive
supply voltage. The bypass capacitors reduce common-mode
perturbations by providing an ac short from the common nodes
(V
COM
) to ground. When busing together the outputs of
multiple AD8151s or when running at high data rates, double
termination of its outputs is recommended to mitigate the
impact of reflections due to open transmission line stubs and
the lumped capacitance of the AD8151 output pins. A possible
connection is shown in
Figure 37; the bypass capacitors provide
an ac short from the common nodes of the termination resistors
to ground. To maintain signal fidelity at high data rates, the
stubs connecting the output pins to the output transmission
lines or load resistors should be as short as possible.
02169-037
R
L
R
L
R
L
R
L
Z
O
Z
O
Z
O
Z
O
V
CC
R
COM
V
COM
OUTyyN
OUTyyP
AD8151
OUTyyN
OUTyyP
AD8151
RECEIVER
Figure 37. Double Termination of AD8151 Outputs
In this case, the output levels are
V
OH
= V
COM
– (¼)I
OUT
R
L
V
OL
= V
COM
– (¾)I
OUT
R
L
V
SWING
= V
OH
– V
OL
= (½)I
OUT
R
L
Output Current Set Pin (REF)
A simplified schematic of the reference circuit is shown in
Figure 38. A single external resistor connected between the REF
pin and V
EE
determines the output current for all output stages.
This feature allows a choice of pull-up networks and trans-
mission line characteristic impedances while still achieving a
nominal output swing of 800 mV. At low data rates, substantial
power savings can be achieved by using lower output swings
and higher load resistances.
02169-038
R
SET
V
EE
V
CC
I
OUT
/20
AD8151
REF
1.2V
Figure 38. Simplified Reference Circuit
The nominal output current is given by the following:
⎟
⎠
⎞
⎜
⎝
⎛
=
SETR
V2.1
20
OUTI
The minimum set resistor is R
SET, MIN
= 960 Ω resulting in
I
OUT, MAX
= 25 mA. The maximum set resistor is R
SET, MAX
= 4.8 kΩ
resulting in I
OUT, MIN
= 5 mA. Nominal 800 mV differential
output swing can be achieved in a 50 Ω load using R
SET
= 1.5 kΩ
(I
OUT
= 16 mA), or in a doubly terminated 75 Ω load using
R
SET
= 1.13 kΩ (I
OUT
= 21.3 mA). To minimize stray capacitance
and avoid the pickup of unwanted signals, the external set
resistor should be located close to the REF pin. Bypassing the
set resistor is not recommended.
Power Supplies
There are several options for the power supply voltages for the
AD8151, as there are two separate sections of the chip that
require power supplies. These are the control logic and the high
speed data paths. Depending on the system architecture, the
voltage levels of these supplies can vary.
Logic Supplies
The control (programming) logic is CMOS and is designed to
interface with any of the standard single-ended logic families
(CMOS or TTL). Its supply voltage pins are V
DD
(Pin 170, logic
positive) and V
SS
(Pin 152, logic ground). In all cases the logic
ground should be connected to the system digital ground. V
DD
should be supplied at between 3.3 V to 5 V to match the supply
voltage of the logic family that is used to drive the logic inputs.
V
DD
should be bypassed to ground with a 0.1 μF ceramic capa-
citor. The absolute maximum voltage from V
DD
to V
SS
is 5.5 V.