Datasheet

AD8151
Rev. B | Page 15 of 40
02169-029
CS INPUTS
ENABLING
OUT[0:16][N:P]
OUTPUTS
INPUT {DATA 2}INPUT {DATA 1}
INPUT {DATA 1}INPUT {DATA 0}
DISABLING
OUT[0:16][N:P]
OUTPUTS
UPDATE INPUTS
WE INPUTS
t
CSU
t
UOT
t
WOT
t
WOD
t
WHU
t
CHU
t
UOE
t
UW
Figure 29. First Rank Write Cycle and Second Rank Update Cycle
Table 8. First Rank Write Cycle and Second Rank Update Cycle
Parameter Mnemonic Function Conditions Min Typ Max Unit
Setup Time t
CSU
Chip select to update T
A
= 25°C 0 ns
Hold Time t
CHU
Chip select from update V
DD
= 5 V 0 ns
Output Enable Times t
UOE
Update to output enable V
CC
= 3.3 V 25 40 ns
t
WOE
Write enable to output enable 25 40 ns
Output Toggle Times t
UOT
Update to output reprogram 25 30 ns
t
WOT
Write enable to output reprogram 25 30 ns
Output Disable Times t
UOD
D
1
Update to output disabled 25 30 ns
t
WOD
Write enable to output disabled 25 30 ns
Setup Time t
WHU
Write enable to update 10 ns
Update Pulse t
UW
Width of update pulse 15 ns
1
Not shown.
02169-030
D[6:0]
OUTPUTS
ADDR 1 ADDR 2
DATA
{ADDR 1}
DATA
{ADDR 2}
CS INPUTS
RE INPUTS
A[4:0]
INPUTS
t
CSR
t
RDE
t
AA
t
RHA
t
CHR
t
RDD
Figure 30. Second Rank Readback Cycle
Table 9. Second Rank Readback Cycle
Parameter Mnemonic Function Conditions Min Typ Max Unit
Setup Time t
CSR
Chip select to read enable T
A
= 25°C 0 ns
Hold Time t
CHR
Chip select from read enable V
DD
= 5 V 0 ns
Read Enable t
RHA
Address from read enable V
CC
= 3.3 V 5 ns
Enable Time t
RDE
Data from read enable 10 kΩ 15 ns
Access Time t
AA
Data from address 20 pF on D[6:0] 15 ns
Release Time t
RDD
Data from read enable Bus 15 30 ns