Datasheet

AD8151
Rev. B | Page 14 of 40
CONTROL INTERFACE TIMING DIAGRAMS
02169-027
A[4:0] INPUTS
t
CSW
t
ASW
t
WP
t
DSW
t
DHW
t
AHW
t
CHW
CS INPUTS
WE INPUTS
D[6:0] INPUTS
Figure 27. First Rank Write Cycle
Table 6. First Rank Write Cycle
Parameter Mnemonic Description Conditions Min Typ Max Unit
Setup Time t
CSW
Chip select to write enable T
A
= 25°C 0 ns
t
ASW
Address to write enable V
DD
= 5 V 0 ns
t
DSW
Data to write enable V
CC
= 3.3 V 15 ns
Hold Time t
CHW
Chip select from write enable 0 ns
t
AHW
Address from write enable 0 ns
t
DHW
Data from write enable 0 ns
Enable Pulse t
WP
Width of write enable pulse 15 ns
02169-028
CS INPUTS
ENABLING
OUT[0:16][N:P]
OUTPUTS
TOGGLE
OUT[0:16][N:P]
OUTPUTS
DISABLING
OUT[0:16][N:P]
OUTPUTS
DATA FROM RANK 1
PREVIOUS RANK 2 DATA
DATA FROM RANK 2
DATA FROM RANK 1
UPDATE INPUTS
t
CHU
t
UW
t
UOT
t
UOD
t
UOE
t
CSU
Figure 28. Second Rank Update Cycle
Table 7. Second Rank Update Cycle
Parameter Mnemonic Function Conditions Min Typ Max Unit
Setup Time t
CSU
Chip select to update T
A
= 25°C 0 ns
Hold Time t
CHU
Chip select from update V
DD
= 5 V ns
Output Enable Times t
UOE
Update to output enable V
CC
= 3.3 V 25 40 ns
Output Toggle Times t
UOT
Update to output reprogram 25 40 ns
Output Disable Times t
UOD
Update to output disabled 25 30 ns
Update Pulse t
UW
Width of update pulse 15 ns