Datasheet

AD8150
Rev. A | Page 18 of 44
01074-029
D[6:0]
OUTPUTS
ADDR 1 ADDR 2
DATA
{ADDR 1}
DATA
{ADDR 2}
CS INPUT
RE INPUT
A[4:0]
INPUTS
t
CSR
t
RDE
t
AA
t
RHA
t
CHR
t
RDD
Figure 29. Second-Rank Readback Cycle
Table 9. Second-Rank Readback Cycle
Symbol Parameter Conditions Min Typ Max Unit
t
CSR
Setup Time Chip select to read enable T
A
= 25°C 0 ns
t
CHR
Hold Time Chip select from read enable V
DD
= 5 V 0 ns
t
RHA
Address from read enable V
CC
= 5 V 5 ns
t
RDE
Enable Time Data from read enable 10 kΩ 15 ns
t
AA
Access Time Data from address 20 pF on D[6:0] 15 ns
t
RDD
Release Time Data from read enable Bus 15 30 ns