Datasheet

AD8150
Rev. A | Page 15 of 44
CONTROL INTERFACE TIMING DIAGRAMS
01074-026
A[4:0] INPUTS
t
CSW
t
ASW
t
WP
t
DSW
t
DHW
t
AHW
t
CHW
CS INPUT
WE INPUT
D[6:0] INPUTS
Figure 26. First-Rank Write Cycle
Table 6. First-Rank Write Cycle
Symbol Parameter Conditions Min Typ Max Unit
t
CSW
Setup Time Chip select to write enable T
A
= 25°C 0 ns
t
ASW
Address to write enable V
DD
= 5 V 0 ns
t
DSW
Data to write enable V
CC
= 5 V 15 ns
t
CHW
Hold Time Chip select from write enable 0 ns
t
AHW
Address from write enable 0 ns
t
DHW
Data from write enable 0 ns
t
WP
Width of Write Enable Pulse 15 ns