Datasheet

AD8145
Rev. A | Page 7 of 24
ABSOLUTE MAXIMUM RATINGS
MAXIMUM POWER DISSIPATION
Table 3.
Parameter Rating
Supply Voltage 12 V
Power Dissipation See Figure 2
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +105°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C
The maximum safe power dissipation in the AD8145 package is
limited by the associated rise in junction temperature (T
J
) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit can change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the AD8145. Exceeding a junction temperature
of 150°C for an extended period can result in changes in the
silicon devices, potentially causing failure.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
The power dissipated in the package (P
D
) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (V
S
) times the
quiescent current (I
S
). The power dissipated due to the load
drive depends on the particular application. For each output, the
power due to load drive is calculated by multiplying the load
current by the associated voltage drop across the device. The
power dissipated due to all of the loads is equal to the sum of
the power dissipation due to each individual load. RMS voltages
and currents must be used in these calculations.
THERMAL RESISTANCE
θ
JA
is specified for the worst-case conditions, that is, θ
JA
is
specified for a device soldered in the circuit board with its
exposed paddle soldered to a pad on the PCB surface, which is
thermally connected to a copper plane.
Airflow increases heat dissipation, effectively reducing θ
JA
. In
addition, more metal directly in contact with the package leads
from metal traces, through-holes, ground, and power planes
reduces the θ
JA
. The exposed paddle on the underside of the
package must be soldered to a pad on the PCB surface, which is
thermally connected to a copper plane to achieve the specified θ
JA
.
Table 4. Thermal Resistance
Package Type θ
JA
θ
JC
Unit
5 mm × 5 mm, 32-Lead LFCSP 47 8.5 °C/W
4.5
0
–40 –20 0 20 40 60 80 100
AMBIENT TEMPERATURE (°C)
MAXIMUM POWER DISSIPATION (W)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
06307-002
Figure 2 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 32-lead LFCSP
(47°C/W) on a JEDEC standard 4-layer board with the underside
paddle soldered to a pad, which is thermally connected to a
PCB plane.
ESD CAUTION
Figure 2. Maximum Power Dissipation vs. Temperature for a 4-Layer Board