Datasheet

AD813
REV. B –17–
Disable Mode Operation
Pulling the voltage on any one of the Disable pins about 2.5 V
down from the positive supply will put the corresponding ampli-
fier into a disabled, powered down, state. In this condition, the
amplifier’s quiescent supply current drops to about 0.5 mA, its
output becomes a high impedance, and there is a high level of
isolation from input to output. In the case of the gain of two
line driver for example, the impedance at the output node will
be about the same as for a 1.4 kΩ resistor (the feedback plus
gain resistors) in parallel with a 12.5 pF capacitor and the input
to output isolation will be about 65 dB at 1 MHz.
Leaving the Disable pin disconnected (floating) will leave the
corresponding amplifier operational, in the enabled state. The
input impedance of the disable pins is about 35 kΩ in parallel
with a few pF. When grounded, about 50 µA flows out of a
disable pin on ±5 V supplies.
Input voltages greater than about 1.5 V peak-to-peak will defeat
the isolation. In addition, large signals (greater than 3 V peak-
to-peak) applied to the output node will cause the output im-
pedance to drop significantly.
When the Disable pins are driven by complementary output
CMOS logic (such as the 74HC04), the disable time is about
80 ns (until the output goes high impedance) and the enable
time is about 100 ns (to low impedance output) on ±15 V sup-
plies. When operated on ±15 V supplies, the disable pins
should be driven by open drain logic. In this case, pull-up resis-
tors from the disable pins to the plus supply will ensure mini-
mum switching time.
75V
75V
75V
75V
V
OUT
75V
CABLE
1
V
IN
1
84V
+5V
464V 590V
7
4
5
6
SELECT1
2
V
IN
2
84V
464V 590V
14
12
13
SELECT2
V
IN
3
84V
3
464V 590V
8
10
9
SELECT3
11
–5V
Figure 55. A Fast Switching 3:1 Video Mux
(Supply Bypassing Not Shown)
Operation Using a Single Supply
The AD813 will operate with total supply voltages from 36 V
down to 2.4 V. With proper biasing (see Figure 52) it can
make an outstanding single supply video amplifier. Since the
input and output voltage ranges extend to within 1 V of the
supply rails, it will handle a 1.3 V peak-to-peak signal on a
single 3.3 V supply, or a 3 V peak-to-peak signal on a single
5 V supply. The small signal 0.1 dB bandwidths will exceed
10 MHz in either case, and the large signal bandwidths will
exceed 6 MHz.
The capacitively coupled cable driver in Figure 52 will achieve
outstanding differential gain and phase errors of 0.05% and 0.05
degrees respectively on a single 5 V supply. Resistor R2, in this
circuit, is selected to optimize the differential gain and phase by
biasing the amplifier in its most linear region.
75V
AD813
4
11
V
IN
R2
12.4kV
V
OUT
75V
+5V
75V
CABLE
C2
1mF
R1
9kV
C1
2mF
C3
30mF
619V 619V
R3
1kV
C
OUT
47mF
Figure 52. Biasing for Single Supply Operation
1
10 1000100
FREQUENCY – MHz
–0.5
–3.0
0.5
0
–1.0
–1.5
–2.0
–2.5
CLOSED-LOOP GAIN – dB
0
–90
–180
–270
PHASE SHIFT – Degrees
–3.5
GAIN
PHASE
V
S
= 5V
G = +2
R
F
= 619V
R
L
= 150V
Figure 53. Closed-Loop Gain and Phase vs. Frequency,
Circuit of Figure 52
10
100
0%
500mV
1V
500mV
50ns
90
V
IN
V
OUT
Figure 54. Pulse Response for the Circuit of Figure 52
with +V
S
= 5 V