Datasheet

AD8139
Rev. B | Page 21 of 24
One way to avoid the input common-mode swing limitation is
to bias V
IN
and V
REF
at midsupply. In this case, V
IN
is 5 V p-p
swinging about a baseline at 2.5 V, and V
REF
is connected to a
low-Z 2.5 V source. V
ICM
now has an amplitude of 2.5 V p-p and
is swinging about 2.5 V. Using the results in Equation 17, V
ACM
is calculated to be equal to V
ICM
because V
OCM
= V
ICM
. Therefore,
V
ACM
swings from 1.25 V to 3.75 V, which is well within the
input common-mode voltage limits of the AD8139. Another
benefit seen in this example is that because V
OCM
= V
ACM
= V
ICM
no wasted common-mode current flows.
Figure 62 illustrates
how to provide the low-Z bias voltage. For situations that do not
require a precise reference, a simple voltage divider suffices to
develop the input voltage to the buffer.
V
IN
0V TO 5V
AD8139
+
–
8
2
1
6
3
4
5
V
OCM
200Ω
324Ω
5
V
200Ω 324Ω
0.1µF
0.1µF
10µF
+
AD8031
+
–
0.1µF
5V
ADR431
2.5V
REFERENCE
TO AD7674 REFBUFIN
04679-053
Figure 62. Low-Z 2.5 V Buffer
Another way to avoid the input common-mode swing limitation is
to use dual power supplies on the AD8139. In this case, the
biasing circuitry is not required.
Bandwidth vs. Closed-Loop Gain
The 3 dB bandwidth of the AD8139 decreases proportionally
to increasing closed-loop gain in the same way as a traditional
voltage feedback operational amplifier. For closed-loop gains
greater than 4, the bandwidth obtained for a specific gain can be
estimated as
)MHz300(,dB3
,
×
+
=−
F
G
G
dmOUT
RR
R
Vf
(20)
or equivalently, β(300 MHz).
This estimate assumes a minimum 90° phase margin for the
amplifier loop, which is a condition approached for gains greater
than 4. Lower gains show more bandwidth than predicted by
the equation due to the peaking produced by the lower
phase margin.
Estimating DC Errors
Primary differential output offset errors in the AD8139 are due
to three major components: the input offset voltage, the offset
between the V
AN
and V
AP
input currents interacting with the
feedback network resistances, and the offset produced by the dc
voltage difference between the input and output common-mode
voltages in conjunction with matching errors in the feedback
network.
The first output error component is calculated as
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
+
=
G
G
F
IO
R
RR
Ve1Vo_
, or equivalently as V
IO
/β (21)
where V
IO
is the input offset voltage. The input offset voltage of the
AD8139 is laser trimmed and guaranteed to be less than 500 µV.
The second error is calculated as
()
F
IO
G
F
F
G
G
G
F
IO
RI
RR
RR
R
RR
Ie2Vo =
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
+
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
+
=
_ (22)
where I
IO
is defined as the offset between the two input bias
currents.
The third error voltage is calculated as
Vo_e3 = enr × (V
ICM
− V
OCM
) (23)
where enr is the fractional mismatch between the two
feedback resistors.
The total differential offset error is the sum of these three error
sources.
Other Impact of Mismatches in the Feedback Networks
The internal common-mode feedback network still forces the
output voltages to remain balanced, even when the R
F
/R
G
feedback
networks are mismatched. However, the mismatch will cause a
gain error proportional to the feedback network mismatch.
Ratio-matching errors in the external resistors degrade the
ability to reject common-mode signals at the V
AN
and V
IN
input
terminals, much the same as with a four-resistor difference
amplifier made from a conventional op amp. Ratio-matching
errors also produce a differential output component that is
equal to the V
OCM
input voltage times the difference between the
feedback factors (βs). In most applications using 1% resistors,
this component amounts to a differential dc offset at the output
that is small enough to be ignored.