Datasheet

AD8134
Rev. A | Page 13 of 20
CALCULATING AN APPLICATION CIRCUIT’S INPUT
IMPEDANCE
The effective input impedance of a circuit such as that in
Figure 30 at V
IP
and V
IN
depends on whether the amplifier is
being driven by a single-ended or differential signal source. For
balanced differential input signals, the differential input
impedance, R
IN, dm
, between the inputs V
IP
and V
IN
is simply
R
IN,dm
= 2 × R
G
= 1.5 kΩ
In the case of a single-ended input signal (for example, if V
IN
is
grounded and the input signal is applied to V
IP
), the input
impedance becomes
()
kΩ125.1
2
1
=
⎟
⎟
⎟
⎟
⎠
⎞
⎜
⎜
⎜
⎜
⎝
⎛
+×
−
=
FG
F
G
IN
RR
R
R
R
The circuit’s input impedance is effectively higher than it would
be for a conventional op amp connected as an inverter because
a fraction of the differential output voltage appears at the inputs
as a common-mode signal, partially bootstrapping the voltage
across the input resistor R
G
.
INPUT COMMON-MODE VOLTAGE RANGE IN
SINGLE-SUPPLY APPLICATIONS
The inputs of the AD8134 are designed to facilitate level-
shifting of ground referenced input signals on a single power
supply. For a single-ended input, this would imply, for example,
that the voltage at V
IN
in Figure 30 would be 0 V when the
amplifier’s negative power supply voltage was also set to 0 V.
It is important to ensure that the common-mode voltage at the
amplifier inputs, V
AP
and V
AN
, stays within its specified range.
Since voltages V
AP
and V
AN
are driven to be essentially equal by
negative feedback, the amplifier’s input common-mode voltage
can be expressed as a single term, V
ACM
. V
ACM
can be calculated as
3
2
ICMOCM
ACM
VV
V
+
=
where V
ICM
is the common-mode voltage of the input signal,
that is,
2
INIP
ICM
VV
V
+
=
.
DRIVING A CAPACITIVE LOAD
A purely capacitive load can react with the output impedance
of the AD8134 to reduce phase margin, resulting in high
frequency ringing in the pulse response. The best way to
minimize this effect is to place a small resistor in series with
each of the amplifier’s outputs to buffer the load capacitance.
OUTPUT PULL-DOWN (OPD)
The AD8134 has an OPD pin that when pulled high
significantly reduces the power consumed while simultaneously
pulling the outputs to within less than 1 V of V
S−
when used
with series diodes (see the
Applications section). The equivalent
schematic of the output in the output pull-down state is shown
in
Figure 31. (The ESD diodes shown in Figure 31 are for ESD
protection and are distinct from the series diodes used with the
output pull-down feature.) See
Figure 18 and Figure 24 for the
output pull-down transient and isolation performance. The
threshold levels for the OPD input pin are referenced to the
positive power supply and are listed in the
Specifications tables.
When the OPD pin is pulled high, the AD8134 enters the
output pull-down state.
V
OUT
V
CC
PULL-DOWN
(OUTPUT IS
PULLED DOWN
WHEN SWITCH
IS CLOSED)
V
S–
V
S+
ESD DIODE
ESD DIODE
04770-006
Figure 31. Output Pull-Down Equivalent Circuit