Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- GENERAL DESCRIPTION
- CONNECTION DIAGRAM
- TABLE OF CONTENTS
- SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
- TYPICAL PERFORMANCE CHARACTERISTICS
- TEST CIRCUITS
- OPERATIONAL DESCRIPTION
- THEORY OF OPERATION
- GENERAL USAGE OF THE AD8132
- DIFFERENTIAL AMPLIFIER WITHOUT RESISTORS (HIGH INPUT IMPEDANCE INVERTING AMPLIFIER)
- OTHER β2 = 1 CIRCUITS
- VARYING β2
- β1 = 0
- ESTIMATING THE OUTPUT NOISE VOLTAGE
- CALCULATING INPUT IMPEDANCE OF THE APPLICATION CIRCUIT
- INPUT COMMON-MODE VOLTAGE RANGE IN SINGLE-SUPPLY APPLICATIONS
- SETTING THE OUTPUT COMMON-MODE VOLTAGE
- DRIVING A CAPACITIVE LOAD
- OPEN-LOOP GAIN AND PHASE
- LAYOUT, GROUNDING, AND BYPASSING
- APPLICATIONS INFORMATION
- OUTLINE DIMENSIONS

AD8132
Rev. I | Page 26 of 32
APPLICATIONS INFORMATION
ANALOG-TO-DIGITAL DRIVER
Many of the newer high speed ADCs are single supply and have
differential inputs. Thus, the driver for these devices is able to
convert from a single-ended signal to a differential signal and
provide output common-mode level shifting in addition to
having low distortion and noise. The AD8132 conveniently
performs these functions when driving the AD9203, a 10-bit,
40 MSPS ADC.
In Figure 73, a 1 V p-p signal drives the input of an AD8132
configured for unity gain. Both the AD8132 and the AD9203 are
powered from a single 3 V supply. A voltage divider biases V
OCM
at midsupply and in turn drives V
OUT, cm
to half of the supply
voltage. This is within the common-mode range of the AD9203.
Between the ADC and the driver is a 1-pole, differential filter that
helps to filter some of the noise and assists the switched-capacitor
inputs of the ADC. Each of the ADC inputs is driven by a 0.5 V p-p
signal that ranges from 1.25 V dc to 1.75 V dc. Figure 72 is an
FFT plot of the performance of the circuit when running at a
clock rate of 40 MSPS and an input frequency of 2.5 MHz.
10
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0
2ND
3RD
4TH
5TH
7TH
8TH
9TH
6TH
f
S
= 40MHz
f
IN
= 2.5MHz
INPUT FREQUENCY (MHz)
OUTPUT (dBc)
FUND
01035-071
Figure 72. FTT Response for AD8132 Driving AD9203
BALANCED CABLE DRIVER
When driving a twisted pair cable, it is desirable to drive only
a pure differential signal onto the line. If the signal is purely
differential (that is, fully balanced), and the transmission line is
twisted and balanced, there is minimum radiation of any signal.
The complementary electrical fields are confined mostly to
the space between the two twisted conductors and does not
significantly radiate out from the cable. The current in the cable
creates magnetic fields that radiate to some degree. However, the
amount of radiation is mitigated by the twists, because for
each twist, the two adjacent twists have an opposite polarity
magnetic field. If the twist pitch is tight enough, these small
magnetic field loops contain most of the magnetic flux, and
the magnetic farfield strength is negligible.
3
V
0.1µF 10µF
+
3V
348Ω
0.1µF
348Ω
49.9Ω
348Ω
24.9Ω
10kΩ
10kΩ
1V p-p
348Ω
60.4Ω
60.4Ω
20pF
20pF
AINN
AINP
AVDD DRVDD
AVSS DRVSS
AD9203
DIGITAL
OUTPUTS
3V
0.1µF
0.1µF
AD8132
8
2
1
3
5
6
4
25
26
28
27
1
2
01035-070
Figure 73. AD8132 Driving AD9203, a 10-Bit, 40 MSPS ADC