Datasheet

AD8117/AD8118
Rev. A | Page 16 of 36
CLK, SER/PAR, WE,
UPDATE, DATA IN,
A[4:0], D[5:0]
DGND
1kΩ
0
6365-015
Figure 16. Logic Input (see also ESD Protection Map,
Figure 18)
V
DD
DGND
DATA OUT
0
6365-016
Figure 17. Logic Output (see also ESD Protection Map,
Figure 18)
V
POS
VNEG
IPn, INn,
OPn, ONn,
VOCM
V
DD
DGND
CLK, RESET,
SER/PAR, WE,
UPDATE,
DATA IN,
DATA OUT,
A[4:0], D[5:0]
06365-017
Figure 18. ESD Protection Map