Datasheet

AD8117/AD8118
Rev. A | Page 13 of 36
TRUTH TABLE AND LOGIC DIAGRAM
Table 9. Operation Truth Table
WE UPDATE CLK
DATA
INPUT
DATA
OUTPUT
RESET
SER
/PAR
Operation/Comment
X X X X X 0 X
Asynchronous reset. All outputs are
disabled. Remainder of logic in 192-bit shift
register is unchanged.
0 X X D0…D5
1
NA in
parallel
mode
1 0
Broadcast. The data on parallel lines D0 to
D5 are loaded into all 32 output address
locations of the 192-bit shift register.
1 X
Data
i
2
Data
i-192
1 0
Serial mode. The data on the serial DATA IN
line is loaded into the serial register. The first
bit clocked into the serial register appears
at DATA OUT 192 clock cycles later.
0 X X D0…D5
1
A0…A4
3
NA in
parallel
mode
1 1
Parallel programming mode. The data on
parallel lines D0 to D5 are loaded into the
shift register location addressed by A0 to A4.
1 0 X X
NA in
parallel
mode
1 X
Switch matrix update. Data in the 192-bit
shift register transfers into the parallel
latches that control the switch array.
1 X X X X 1 1 No change in logic.
1
D0…D5: data bits.
2
Data
i
: serial data.
3
A0…A4: address bits.