Datasheet

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600 MHz, 32 × 32 Buffered

Analog Crosspoint Switch

AD8117/AD8118

Rev. A

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FEATURES

High channel count, 32 × 32 high speed, non-blocking

switch array

Differential or single-ended operation

Differential G = +1 (AD8117) or G = +2 (AD8118)

Flexible power supplies

Single +5 V supply, or dual ±2.5 V supplies

Serial or parallel programming of switch array

High impedance output disable allows connection of

multiple devices with minimal loading on output bus

Excellent video performance

>50 MHz 0.1 dB gain flatness

0.05%/0.05° differential gain/phase error (R

= 150 Ω)

Excellent ac performance

Bandwidth: 600 MHz

Slew rate: 1800 V/μs

Settling time: 2.5 ns to 1%

Low power of 2.5 W

Low all hostile crosstalk

< −70 dB @ 5 MHz

< −43 dB @ 600 MHz

Reset pin allows disabling of all outputs (connected through

a capacitor to ground provides power-on reset capability)

304-ball BGA package (31 mm × 31 mm)

APPLICATIONS

Routing of high speed signals including

RGB and component video routing

KVM

Compressed video (MPEG, wavelet)

Data communications

FUNCTIONAL BLOCK DIAGRAM

INPUT

RECEIVER

G = +1*

G = +2**

OUTPUT

BUFFER

G = +1

1024

SET INDIVIDUAL, OR

RESET ALL OUTPUTS TO OFF

ENABLE/DISABLE

192

VPOS VNEG VOCM

32 INPUT PAIRS

RESET

UPDATE

CLK

DATA IN

SER/PAR

D0 D1 D2 D3 D4 D5

DD DGND

DATA

OUT

32 OUTPUT PAIRS

SWITCH

MATRIX

192

AD8117/

AD8118

192-BIT SHIFT REGISTER

WITH 6-BIT

PARALLEL LOADING

PARALLEL LATCH

DECODE

32 × 6:32 DECODERS

06365-001

*AD8117 ONLY

**AD8118 ONLY

Figure 1.

GENERAL DESCRIPTION

The AD8117/AD8118 are high speed, 32 × 32 analog crosspoint

switch matrices. They offer 600 MHz bandwidth and slew rate of

1800 V/µs for high resolution computer graphics (RGB) signal

switching. With less than −70 dB of crosstalk and −90 dB

isolation (@ 5 MHz), the AD8117/AD8118 are useful in many

high speed applications. The 0.1 dB flatness greater than

50 MHz makes the AD8117/AD8118 ideal for composite video

switching.

The AD8117/AD8118 include 32 independent output buffers

that can be placed into a high impedance state for paralleling

crosspoint outputs so that off-channels present minimal loading

to an output bus. The AD8117 has a differential gain of +1,

while the AD8118 has a differential gain of +2 for ease of use in

back-terminated load applications. They operate as fully

differential devices or can be configured for single-ended

operation. Either a single +5 V supply or dual ±2.5 V supplies

can be used, while consuming only 500 mA of idle current with

all outputs enabled. The channel switching is performed via a

double-buffered, serial digital control (which can accommodate

daisy chaining of several devices), or via a parallel control,

allowing updating of an individual output without reprogram-

ming the entire array.

The AD8117/AD8118 are packaged in a 304-ball BGA package

and are available over the extended industrial temperature

range of −40°C to +85°C.

Summary of content (36 pages)

PAGE 1
600 MHz, 32 × 32 Buffered Analog Crosspoint Switch AD8117/AD8118 FUNCTIONAL BLOCK DIAGRAM D0 D1 D2 D3 D4 D5 VDD DGND AD8117/ AD8118 A0 A1 A2 A3 A4 SER/PAR 1 0 DATA IN 192-BIT SHIFT REGISTER WITH 6-BIT PARALLEL LOADING DATA OUT SET INDIVIDUAL, OR RESET ALL OUTPUTS TO OFF WE CLK 192 UPDATE PARALLEL LATCH RESET 192 DECODE 32 × 6:32 DECODERS INPUT RECEIVER G = +1* G = +2** 1024 32 OUTPUT BUFFER G = +1 2 ENABLE/DISABLE 2 32 INPUT PAIRS High channel count, 32 × 32 high speed, non-blocking swi
PAGE 2
AD8117/AD8118 TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................7 Applications....................................................................................... 1 Pin Configuration and Function Descriptions..............................8 Functional Block Diagram ..............................................................
PAGE 3
AD8117/AD8118 SPECIFICATIONS VS = ±2.5 V at TA = 25°C, RL, diff = 200 Ω, VOCM = 0 V, differential I/O mode, unless otherwise noted. Table 1.
PAGE 4
AD8117/AD8118 Parameter SWITCHING CHARACTERISTICS Enable On Time Switching Time, 2 V Step Switching Transient (Glitch) POWER SUPPLIES Supply Current Supply Voltage Range PSRR OPERATING TEMPERATURE RANGE Temperature Range θJA θJC Conditions Min AD8117/AD8118 Typ Max 50% update to 1% settling 50% update to 1% settling Differential 100 100 40 VPOS, outputs enabled, no load Outputs disabled VNEG, outputs enabled, no load Outputs disabled VDD, outputs enabled, no load 500 200 500 200 Unit ns ns mV p-p
PAGE 5
AD8117/AD8118 TIMING CHARACTERISTICS (SERIAL MODE) Specifications subject to change without notice. Table 2.
PAGE 6
AD8117/AD8118 TIMING CHARACTERISTICS (PARALLEL MODE) Specifications subject to change without notice. Table 4.
PAGE 7
AD8117/AD8118 ABSOLUTE MAXIMUM RATINGS POWER DISSIPATION Table 6.
PAGE 8
AD8117/AD8118 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A VPOS VPOS VPOS VPOS OP17 ON17 OP19 ON19 OP21 ON21 OP23 ON23 OP25 ON25 OP27 ON27 OP29 ON29 OP31 ON31 VPOS VPOS VPOS A B VPOS VPOS VPOS OP16 ON16 OP18 ON18 OP20 ON20 OP22 ON22 OP24 ON24 OP26 ON26 OP28 ON28 OP30 ON30 VPOS VPOS VPOS VPOS B C VPOS VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPO
PAGE 9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 23 22 21 A VPOS VPOS VPOS ON31 OP31 ON29 OP29 ON27 OP27 ON25 OP25 ON23 OP23 ON21 OP21 ON19 OP19 ON17 OP17 VPOS VPOS VPOS VPOS A B VPOS VPOS VPOS VPOS ON30 OP30 ON28 OP28 ON26 OP26 ON24 OP24 ON22 OP22 ON20 OP20 ON18 OP18 ON16 OP16 VPOS VPOS VPOS B C VPOS VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VPOS
PAGE 10
AD8117/AD8118 Ball No.
PAGE 11
AD8117/AD8118 Ball No. J21 J22 J23 K1 K2 K3 K4 K20 K21 K22 K23 L1 L2 L3 L4 L20 L21 L22 L23 M1 M2 M3 M4 M20 M21 M22 M23 N1 N2 N3 N4 N20 N21 N22 N23 P1 P2 P3 P4 P20 P21 P22 P23 R1 R2 R3 R4 R20 R21 R22 R23 T1 Mnemonic VNEG IN21 IP20 IN5 IP6 VNEG DATA IN WE VNEG IP21 IN22 IP7 IN6 VPOS SER/PAR D5 VPOS IN23 IP22 IN7 IP8 VPOS A4 D4 VPOS IP23 IN24 IP9 IN8 VPOS A3 D3 VPOS IN25 IP24 IN9 IP10 VNEG A2 D2 VNEG IP25 IN26 IP11 IN10 VNEG A1 D1 VNEG IN27 IP26 IN11 Description Analog Negative Power Supply.
PAGE 12
AD8117/AD8118 Ball No. Y19 Mnemonic VOCM Y20 Y21 Y22 Y23 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 VNEG VPOS IP31 VPOS VPOS VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VPOS VPOS VPOS VPOS OP0 ON0 OP2 ON2 OP4 ON4 Description Output Common-Mode Reference Supply. Analog Negative Power Supply. Analog Positive Power Supply.
PAGE 13
AD8117/AD8118 TRUTH TABLE AND LOGIC DIAGRAM Table 9. Operation Truth Table WE X UPDATE X CLK X DATA INPUT X DATA OUTPUT X 0 X X D0…D5 1 1 X NA in parallel mode Datai-192 0 X X D0…D51 A0…A4 3 1 0 X X 1 X X X Datai 2 NA in parallel mode NA in parallel mode X SER/PAR RESET 0 X 1 0 1 0 1 1 1 X 1 1 1 D0…D5: data bits. Datai: serial data. 3 A0…A4: address bits. 2 Rev. A | Page 13 of 36 Operation/Comment Asynchronous reset. All outputs are disabled.
PAGE 14
OUTPUT ADDRESS A0 A1 A2 A3 A4 5 TO 32 DECODER CLK WE DATA IN (SERIAL) Figure 7. Logic Diagram Rev.
PAGE 15
AD8117/AD8118 I/O SCHEMATICS IPn 1.3pF 2500Ω 1.3pF 2500Ω 06365-008 INn 06365-011 0.3pF OPn, ONn Figure 12. AD8117/AD8118 Receiver Simplified Equivalent Circuit When Driving Differentially Figure 8. AD8117/AD8118 Enabled Output (see also ESD Protection Map, Figure 18) OPn IPn 3.4pF 3.33kΩ AD8117 G = +1 3.76kΩ AD8118 G = +2 1.6pF 30kΩ 06365-012 0.4pF INn 3.4pF 06365-009 ONn Figure 13. AD8117/AD8118 Receiver Simplified Equivalent Circuit When Driving Single-Ended Figure 9.
PAGE 16
AD8117/AD8118 VPOS 1kΩ DGND VNEG VDD 06365-016 DATA OUT DGND DGND Figure 18. ESD Protection Map Figure 16. Logic Input (see also ESD Protection Map, Figure 18) Figure 17. Logic Output (see also ESD Protection Map, Figure 18) Rev.
PAGE 17
AD8117/AD8118 TYPICAL PERFORMANCE CHARACTERISTICS VS = ±2.5 V at TA = 25°C, RL, diff = 200 Ω, VOCM = 0 V, differential I/O mode, unless otherwise noted. 400 10 8 AD8118 350 6 300 250 2 COUNT GAIN (dB) 4 AD8117 0 –2 200 150 –4 100 –6 1 100 10 1000 FREQUENCY (MHz) 0 06365-018 –10 540 620 640 660 680 700 AD8118 6 4 2 AD8117 0 –2 –4 –6 1 10 1000 100 FREQUENCY (MHz) –2 –3 06365-019 –8 –1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 NUMBER OF ENABLED CHANNELS Figure 20.
PAGE 18
AD8117/AD8118 –15 0 DIFFERENTIAL OUT DIFFERENTIAL IN/OUT VNEG AGGRESSOR –25 –20 –35 PSR (dB) –55 CROSSTALK (dB) VPOS AGGRESSOR –45 VOCM AGGRESSOR –65 –40 –60 –75 –80 1 10 100 1000 FREQUENCY (MHz) –100 300k 06365-024 –95 0.1 10M 0 SINGLE-ENDED OUT 0 DIFFERENTIAL IN/OUT –20 –5 CROSSTALK (dB) VOCM AGGRESSOR –10 PSR (dB) 1G Figure 28. AD8117 Crosstalk, One Adjacent Channel 5 –15 –20 –25 100M FREQUENCY (Hz) Figure 25.
PAGE 19
AD8117/AD8118 0 0 SINGLE-ENDED IN/OUT –20 CROSSTALK (dB) –40 –60 –40 –60 10M 100M 1G FREQUENCY (Hz) –100 300k 06365-071 1M 0 DIFFERENTIAL IN/OUT CROSSTALK (dB) SINGLE-ENDED IN/OUT –40 –60 –80 10M 100M 1G FREQUENCY (Hz) –100 300k 06365-029 1M 10M 100M 1G FREQUENCY (Hz) Figure 35. AD8118 Crosstalk, All Hostile, Single-Ended Figure 32.
PAGE 20
AD8117/AD8118 0 30k SINGLE-ENDED IN/OUT 25k OUTPUT IMPEDANCE (Ω) –40 –60 –80 20k 15k 10k 5k 10M 100M 1G 2G FREQUENCY (Hz) 0 100k 06365-032 1M 10M 100M 1G FREQUENCY (Hz) Figure 37. AD8117 Crosstalk, Off Isolation, Single-Ended 6k 1M 06365-035 FEEDTHROUGH (dB) –20 –100 300k DIFFERENTIAL OUT Figure 40.
PAGE 21
AD8117/AD8118 3 1.5 0.20 UPDATE 0.15 1.0 2 0.5 1 0 0 VOUT (V, DIFF) VOUT (V, SE) N-CHANNEL 0.05 0 –0.05 P-CHANNEL –1 –0.5 –0.10 –1.0 UPDATE (V) 0.10 VOUT –2 –0.15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TIME (ns) –1.5 –40 –20 0 20 40 60 80 –3 120 100 06365-041 0 06365-038 –0.20 TIME (ns) Figure 46. AD8117 Switching Time Figure 43. AD8117 Small Signal Pulse Response, Single-Ended, 200 mV p-p 2.0 1.5 2 5000 1 4000 0 3000 0.5 0 –0.
PAGE 22
AD8117/AD8118 0.014 5 DIFFERENTIAL PHASE ERROR (%) 0.012 OFFSET (mV) 4 3 2 1 0.010 0.008 0.006 0.004 0.002 0 0 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (ºC) –0.004 –700 06365-044 0 –40 –30 –20 –10 Figure 49. AD8117 VOS vs. Temperature in Broadcast Mode –500 –300 –100 100 300 500 700 VIN, DIFF (mV) 06365-047 –0.002 Figure 52. AD8117 Phase vs. DC Voltage, Carrier Frequency = 3.58 MHz, Subcarrier Amplitude = 600 mV p-p, Differential 50 2.0 40 1.5 10pF 5pF 1.
PAGE 23
AD8117/AD8118 IPOS AND INEG (BROADCAST) 2.4 0.6 1.2 0.4 0.8 0.4 VOUT 300 500 200 10 30 50 70 90 110 130 –0.4 150 100 –35 –25 –15 –5 TIME (ns) 15 25 35 45 55 65 75 85 400 95 TEMPERATURE (°C) Figure 58. AD8117, AD8118 Quiescent Supply Currents vs. Temperature Figure 55. AD8117 Enable Time UPDATE 950 500 2.8 1.4 1.2 5 IPOS, INEG 2.4 900 450 850 1.6 1.2 0.6 0.4 0.8 0.2 0.4 IPOS AND INEG (mA) VOUT 0.8 UPDATE (V) 2.0 1.
PAGE 24
AD8117/AD8118 5 2.0 4 1.5 VOUTP 1.0 2 1 VOUT (V, SE) 0 –1 0.5 VINP 0 –0.5 –2 –1.0 –3 0 1 2 3 4 5 6 7 TIME (ns) –2.0 06365-056 –5 0 300 400 500 600 700 Figure 63. AD8118 Overdrive Recovery, Single-Ended 2.5 –30 VINP VOUT = 2V p-p, DIFF –40 VOUTP 1.5 200 TIME (ns) Figure 61. AD8117 Settling Time (Zoom) 2.0 100 06365-069 –1.5 –4 –50 DISTORTION (dBc) 1.0 0.5 0 –0.5 –1.0 THIRD HARMONIC –60 –70 SECOND HARMONIC –80 –1.5 VOUTN –2.0 –90 VINN –2.
PAGE 25
AD8117/AD8118 THEORY OF OPERATION The AD8117/AD8118 are fully differential crosspoint arrays with 32 outputs, each of which can be connected to any one of 32 inputs. Organized by output row, 32 switchable input transconductance stages are connected to each output buffer to form 32-to-1 multiplexers. There are 32 of these multiplexers, each with its inputs wired in parallel, for a total array of 1024 transconductance stages forming a multicast-capable crosspoint switch.
PAGE 26
AD8117/AD8118 APPLICATIONS PROGRAMMING The AD8117/AD8118 have two options for changing the programming of the crosspoint matrix. In the first option, a serial word of 192 bits can be provided that updates the entire matrix each time. The second option allows for changing the programming of a single output via a parallel interface.
PAGE 27
AD8117/AD8118 Reset When powering up the AD8117/AD8118, it is usually desirable to have the outputs come up in the disabled state. The RESET pin, when taken low, causes all outputs to be in the disabled state. However, the UPDATE signal does not reset all registers in the AD8117/AD8118. This is important when operating in the parallel programming mode. Refer to the Parallel Programming Description section for information about programming internal registers after power-up.
PAGE 28
AD8117/AD8118 the linear operating range of the AD8117/AD8118 receiver. This common-mode range can extend rail-to-rail, provided the differential signal swing is small enough to avoid forward biasing the ESD diodes (it is safest to keep the common mode plus differential signal excursions within the supply voltages of the part). See the Specifications section for guaranteed input range. The differential output of the AD8117/AD8118 receiver is linear for a peak of 1.4 V of output voltage difference (1.
PAGE 29
AD8117/AD8118 Differential Gain The specified signal path gain of the AD8117/AD8118 refers to its differential gain. For the AD8117, the gain of +1 means that the difference in voltage between the two output terminals is equal to the difference applied between the two input terminals. For the AD8118, the ratio of output difference voltage to applied input difference voltage is +2. and termination of the output trace or cable.
PAGE 30
AD8117/AD8118 Single-Ended Gain The AD8117/AD8118 operate as a closed-loop differential amplifier. The primary control loop forces the difference between the output terminals to be a ratio of the difference between the input terminals. One output increases in voltage, while the other decreases an equal amount to make the total difference correct. The average of these output voltages is forced to be equal to the voltage on the VOCM terminal by a second control loop.
PAGE 31
AD8117/AD8118 VPOS operation, as there is a common-mode to differential gain conversion that becomes greater at higher frequencies. IOUTPUT, QUIESCENT During operation of the AD8117/AD8118, transient currents flow into the VOCM net from the amplifier control loops. Although the magnitude of these currents are small (10 μA to 20 μA per output), they can contribute to crosstalk if they flow through significant impedances. Driving VOCM with a low impedance, low noise source is desirable.
PAGE 32
AD8117/AD8118 Short-Circuit Output Conditions Although there is short-circuit current protection on the AD8117/AD8118 outputs, the output current can reach values of 80 mA into a grounded output. Any sustained operation with too many shorted outputs can exceed the maximum die temperature and can result in device failure (see the Absolute Maximum Ratings section).
PAGE 33
AD8117/AD8118 there is only one way to drive a test signal into all 31 other inputs in parallel. Each of these cases is legitimately different from the others and might yield a unique value, depending on the resolution of the measurement system, but it is hardly practical to measure all these terms and then specify them. In addition, this describes the crosstalk matrix for just one input channel. A similar crosstalk matrix can be proposed for every other input.
PAGE 34
AD8117/AD8118 From a circuit standpoint, this output crosstalk mechanism looks like a transformer with a mutual inductance between the windings that drive a load resistor. For low frequencies, the magnitude of the crosstalk is given by ⎛ s ⎞⎟ XT = 20 log 10 ⎜ M XY × ⎜ RL ⎟⎠ ⎝ where: MXY is the mutual inductance of Output X to Output Y. RL is the load resistance on the measured output. This crosstalk mechanism can be minimized by keeping the mutual inductance low and increasing RL.
PAGE 35
AD8117/AD8118 If multiple AD8117/AD8118s are to be driven in parallel, a flyby input termination scheme is very useful, but the distance from each AD8117/AD8118 input to the driven input transmission line is a stub that should be minimized in length and parasitics using the discussed guidelines. as trace widths become large. In most cases, the best practical solution is to place the half-characteristic impedance resistor as close as possible (preferably less than 1.
PAGE 36
AD8117/AD8118 OUTLINE DIMENSIONS A1 CORNER INDEX AREA 31.00 BSC SQ 23 6 4 2 22 20 18 16 14 12 10 8 21 19 17 15 13 11 9 5 3 7 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC BALL A1 INDICATOR 27.94 BSC SQ TOP VIEW BOTTOM VIEW 1.27 BSC DETAIL A DETAIL A *1.765 MAX 1.07 0.99 0.92 0.70 0.63 0.56 0.10 MIN COPLANARITY 0.20 SEATING PLANE *COMPLIANT TO JEDEC STANDARDS MO-192-BAN-2 WITH THE EXCEPTION TO PACKAGE HEIGHT. 022206-A 0.25 MIN (4 ) 0.90 0.75 0.60 BALL DIAMETER Figure 74.