Datasheet

AD8116
–3–
REV. B
TIMING CHARACTERISTICS
Limit
Parameter Symbol Min Typ Max Unit
Data Setup Time t
1
20 ns
CLK Pulsewidth t
2
100 ns
Data Hold Time t
3
20 ns
CLK Pulse Separation t
4
100 ns
CLK to UPDATE Delay t
5
0ns
UPDATE Pulsewidth t
6
50 ns
CLK to DATA OUT Valid t
7
200 ns
Propagation Delay, UPDATE to Switch On or Off – 50 ns
Data Load Time, CLK = 5 MHz – 16 µs
CLK, UPDATE Rise and Fall Times – 100 ns
RESET Time – 200 ns
LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE
1
0
1
0
DATA IN
CLK
1 = LATCHED
UPDATE
0 = TRANSPARENT
DATA OUT
OUT15 (D4) OUT15 (D3) OUT00 (D0)
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURING LOW LEVEL
t
1
t
3
t
7
t
2
t
4
t
6
t
5
CLOCK
DATA IN
UPDATE
12 34 5 67 8 910 15 20 25 75 79
T = 0
INCREASING TIME
ENABLE OUTPUT 15 ENABLE OUTPUT 14
CONNECT TO
INPUT 01
DISABLE OUTPUT 13
DON’T CARE
ENABLE OUTPUT 12
CONNECT TO
INPUT 15
CONNECT TO
INPUT 03
CONNECT TO
NPUT 00
ENABLE OUTPUT 11
ENABLE OUTPUT 00
CONNECT TO
INPUT 00
0
Figure 2. Timing Diagram and Programming Example
Table I. Logic Levels
V
IH
V
IL
V
OH
V
OL
I
IH
I
IL
I
OH
I
OL
CLK, DATA IN, CLK, DATA IN, DATA OUT DATA OUT CLK, DATA IN, CLK, DATA IN, DATA OUT DATA OUT
CE, UPDATE CE, UPDATE CE, UPDATE CE, UPDATE
2.0 V min 0.8 V max 2.7 V min 0.5 V max 20 µA max –400 µA min –400 µA max 3.0 mA min