Datasheet
AD8114/AD8115
Rev. B | Page 7 of 32
Table 6. Operation Truth Table
CE UPDATE
CLK DATA IN DATA OUT
RESET
SER
/
PAR
Operation/Comment
1 X X X X X X No change in logic.
0 1
f
Data
i
Data
i-80
1 0
The data on the serial DATA IN line is loaded into
serial register. The first bit clocked into the serial register
appears at DATA OUT 80 clocks later.
0 1
f
D0…D4,
A0… A3
NA in parallel mode 1 1
The data on the parallel data lines, D0 to D4, are
loaded into the 80 bit serial shift register location
addressed by A0 to A3.
0 0 X X X 1 X
Data in the 80-bit shift register transfers into the
parallel latches that control the switch array.
Latches are transparent.
X X X X X 0 X
Asynchronous operation. All outputs are disabled.
Remainder of logic is unchanged.
D
CLK
Q
4 TO 16 DECODER
A0
A1
A2
CLK
16
256
DATA IN
(SERIAL)
(OUTPUT
ENABLE)
SER/PAR
CE
UPDATE
OUT0 EN
DATA
OUT
PARALLEL
DATA
D
Q
CLK
D
Q
CLK
D
Q
CLK
D
Q
CLK
D1
D2
D3
D
Q
CLK
D
Q
CLK
D
Q
CLK
D
Q
CLK
D
Q
CLK
OUT1 EN
OUT2 EN
OUT3 EN
OUT4 EN
OUT5 EN
OUT6 EN
OUT7 EN
D
LE
QCLR
OUT15
EN
OUTPUT ENABLESWITCH MATRIX
S
D1
Q
D0
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
D
Q
CLK
S
D1
Q
D0
D4
DECODE
D
LE
QCLR
OUT0
EN
D
LE
OUT0
B0
Q
D
LE
Q
OUT0
B1
D
LE
Q
OUT0
B2
D
LE
Q
OUT0
B3
D
LE
OUT1
B0
Q
D
LE
QCLR
OUT14
EN
D
LE
OUT15
B0
Q
D
LE
OUT15
B1
Q
D
LE
OUT15
B2
Q
D
Q
CLK
S
D1
Q
D0
S
D1
Q
D0
D
LE
OUT15
B3
Q
S
D1
Q
D0
OUT8 EN
OUT9 EN
OUT10 EN
OUT11 EN
OUT12 EN
OUT13 EN
OUT14 EN
OUT15 EN
A3
OUTPUT
ADDRESS
RESET
(OUTPUT ENABLE)
01070-011
Figure 4. Logic Diagram