Datasheet

AD8114/AD8115
Rev. B | Page 5 of 32
TIMING CHARACTERISTICS (SERIAL)
Table 2. Timing Characteristics
Parameter Symbol Min Typ Max Unit
Serial Data Setup Time t
1
20 ns
CLK Pulse Width t
2
100 ns
Serial Data Hold Time t
3
20 ns
CLK Pulse Separation, Serial Mode t
4
100 ns
CLK to UPDATE Delay
t
5
0 ns
UPDATE Pulse Width
t
6
50 ns
CLK to DATA OUT Valid, Serial Mode t
7
200 ns
Propagation Delay, UPDATE to Switch On or Off
– 50 ns
Data Load Time, CLK = 5 MHz, Serial Mode – 16 µs
CLK, UPDATE Rise and Fall Times
– 100 ns
RESET Time
– 200 ns
Table 3. Logic Levels
V
IH
V
IL
V
OH
V
OL
I
IH
I
IL
I
OH
I
OL
RESET, SER/PAR
CLK, DATA IN,
CE, UPDATE
RESET, SER/PAR
CLK, DATA IN,
CE, UPDATE
DATA OUT DATA OUT
RESET, SER/PAR
CLK, DATA IN,
CE, UPDATE
RESET, SER/PAR
CLK, DATA IN,
CE, UPDATE
DATA OUT DATA OUT
2.0 V min 0.8 V max 2.7 V min 0.5 V max 20 µA max −400 µA min −400 µA max 3.0 mA min
LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE
1
0
1
0
DATA IN
CLK
1 = LATCHED
0 = TRANSPAREN
T
DATA OUT
OUT7 (D4)
OUT7 (D3)
OUT00 (D0)
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURING LOW LEVEL
t
7
t
1
t
3
t
6
t
2
t
4
t
5
UPDATE
01070-002
Figure 2. Timing Diagram, Serial Mode