Datasheet

AD8114/AD8115
Rev. B | Page 10 of 32
Table 8. Pin Function Descriptions
Pin No. Mnemonic Pin Description
58, 60, 62, 64, 66, 68, 70, 72,
4, 6, 8, 10, 12, 14, 16, 18
INxx Analog Inputs. xx = Channels 00 through 15.
96 DATA IN Serial Data Input, TTL Compatible.
97 CLK Clock, TTL Compatible. Falling edge triggered.
98 DATA OUT Serial Data Out, TTL Compatible.
95
UPDATE Enable (Transparent) Low. Allows serial register to connect directly to switch matrix.
Data latched when high.
100
RESET
Disable Outputs, Active Low.
99
CE
Chip Enable, Enable Low. Must be low to clock in and latch data.
94
SER/PAR
Selects Serial Data Mode, Low or Parallel Data Mode, High. Must be connected.
53, 51, 49, 47, 45, 43, 41, 39,
37, 35, 33, 31, 29, 27, 25, 23
OUTyy Analog Outputs. yy = Channels 00 through 15.
3, 5, 7, 9, 11, 13, 15, 17, 19, 57,
59, 61, 63, 65, 67, 69, 71, 73
AGND Analog Ground for Inputs and Switch Matrix. Must be connected.
1, 75 DVCC +5 V for Digital Circuitry.
2, 74 DGND Ground for Digital Circuitry.
20, 56 AVEE −5 V for Inputs and Switch Matrix.
21, 55 AVCC +5 V for Inputs and Switch Matrix.
54, 50, 46, 42, 38, 34, 30, 26, 22 AVCCxx/yy +5 V for Output Amplifier that is Shared by Channels xx and yy. Must be connected.
52, 48, 44, 40, 36, 32, 28, 24 AVEExx/yy –5 V for Output Amplifier that is Shared by Channels xx and yy. Must be connected.
84 A0 Parallel Data Input, TTL Compatible (output select LSB).
83 A1 Parallel Data Input, TTL Compatible (output select).
82 A2 Parallel Data Input, TTL Compatible (output select).
81 A3 Parallel Data Input, TTL Compatible (output select MSB).
80 D0 Parallel Data Input, TTL Compatible (input select LSB)
79 D1 Parallel Data Input, TTL Compatible (input select).
78 D2 Parallel Data Input, TTL Compatible (input select).
77 D3 Parallel Data Input, TTL Compatible (input select MSB).
76 D4 Parallel Data Input, TTL Compatible (output enable).
85 to 93 NC No Connect.