Datasheet

REV. A
AD8113
–11–
CAP LOAD – pF
SERIES RESISTANCE – ⍀
0
300
35
250
200
150
100
50
0
51015202530
V
S
= ⴞ12V
R
L
= 600⍀
V
S
= ⴞ5V
R
L
= 150⍀
TPC 13. Cap Load vs. Series Resistance for Less than 30%
Overshoot
IMPEDANCE – ⍀
1
100
1k
10k
10
FREQUENCY – MHz
0.1 101 100 1000
TPC 14. Disabled Output Impedance vs. Frequency,
V
S
= ± 5 V
IMPEDANCE – ⍀
1
100
1k
10
FREQUENCY – MHz
0.1 101 100 1000
0.1
TPC 15. Enabled Output Impedance vs. Frequency,
V
S
= ± 5 V
INPUT
OUTPUT
5ns/DIV
051015 20 25 30 35 40 45 50
0.1%/DIV
OUTPUT
– INPUT
2
TPC 16. Settling Time to 0.1%, 2 V Step, V
S
= ± 5 V,
R
L
= 150 Ω
IMPEDANCE – ⍀
1
100
1k
10k
10
FREQUENCY – MHz
0.1 101 100 1000
TPC 17. Disabled Output Impedance vs. Frequency,
V
S
= ± 12 V
IMPEDANCE – ⍀
1
100
1k
10
FREQUENCY – MHz
0.1 101 100 1000
0.1
TPC 18. Enabled Output Impedance vs. Frequency,
V
S
= ± 12 V