Datasheet

ManualsBrandsANALOG DEVICES ManualsInterface ICsInterface IC - analogue switches LQFP 100

AD8112

Rev. 0 | Page 8 of 28

Table 7. Operation Truth Table

UPDATE

CLK DATA IN DATA OUT

RESET

SER

/PAR

Operation/Comment

1 X X X X X X No change in logic.

0 1

Data

i-80

1 0

The data on the serial DATA IN line is loaded into serial register.

The first bit clocked into the serial register appears at DATA OUT

80 clocks later.

0 1

D0 ... D4,

A0 ... A2

N/A in

Parallel

Mode

1 1

The data on the parallel data lines, D0 to D4, is loaded into the

80-bit serial shift register location addressed by A0 to A2.

0 0 X X X 1 X

Data in the 80-bit shift register transfers into the parallel

latches that control the switch array. Latches are transparent.

X X X X X 0 X

Asynchronous operation. All outputs are disabled. Remainder

of logic is unchanged.

CLK

3-TO-16 DECODER

CLK

UPDATE

128

DATA IN

(SERIAL)

(OUTPUT

ENABLE)

SER/PAR

RESET

(OUTPUT ENABLE)

OUT00 EN

DATA OUT

PARALLEL

DATA

CLK

CLK CLK CLK

CLK

CLK CLK CLK CLK

OUT01 EN

OUT02 EN

OUT03 EN

OUT04 EN

OUT05 EN

OUT06 EN

OUT07 EN

DLE

QCLR

OUT07

OUTPUT ENABLE

SWITCH MATRIX

CLK

DECODE

DLE

QCLR

OUT00

DLE

OUT00

DLE

OUT00

DLE

OUT00

DLE

OUT00

DLE

OUT01

DLE

QCLR

OUT06

DLE

OUT07

DLE

OUT07

DLE

OUT07

CLK

DLE

OUT07

OUTPUT

ADDRESS

QDQDQDQDQ DQ DQDQ DQDQDQ

06523-005

Figure 5. Logic Diagram