Datasheet

AD8112
Rev. 0 | Page 6 of 28
TIMING CHARACTERISTICS (PARALLEL)
Table 4.
Limit
Parameter Symbol Min Max Unit
Data Setup Time t
1
20 ns
CLK Pulse Width t
2
100 ns
Data Hold Time t
3
20 ns
CLK Pulse Separation t
4
100 ns
CLK to UPDATE Delay
t
5
0 ns
UPDATE Pulse Width
t
6
50 ns
Propagation Delay, UPDATE to Switch On or Off
50 ns
CLK, UPDATE Rise and Fall Times
100 ns
RESET Time
200 ns
t
5
t
6
t
4
t
2
t
1
t
3
1
0
1
0
1=LATCHED
CLK
D0 TO D4
A0 TO A2
0
= TRANSPARENT
UPDATE
0
6523-003
Figure 3. Timing Diagram, Parallel Mode
Table 5. Logic Levels
Pins V
IH
V
IL
V
OH
V
OL
I
IH
I
IL
I
OH
I
OL
RESET, SER/PAR,
CLK, D0, D1, D2,
D3, D4, A0, A1, A2,
CE, UPDATE
2.0 V min 0.8 V max 20 μA max −400 μA min
DATA OUT 2.7 V min 0.5 V max −400 μA max 3.0 mA min