Datasheet

AD8112
Rev. 0 | Page 5 of 28
TIMING CHARACTERISTICS (SERIAL)
Table 2.
Limit
Parameter Symbol Min Typ Max Unit
Serial Data Setup Time t
1
20 ns
CLK Pulse Width t
2
100 ns
Serial Data Hold Time t
3
20 ns
CLK Pulse Separation, Serial Mode t
4
100 ns
CLK to UPDATE Delay
t
5
0 ns
UPDATE Pulse Width
t
6
50 ns
CLK to DATA OUT Valid, Serial Mode t
7
200 ns
Propagation Delay, UPDATE to Switch On or Off
50 ns
Data Load Time, CLK = 5 MHz, Serial Mode 16 μs
CLK, UPDATE Rise and Fall Times
100 ns
RESET Time
200 ns
1
0
1
0
1 = LATCHED
0 = TRANSPARENT
DATA OUT
CLK
DATA IN
t
2
t
4
t
1
t
3
t
7
t
5
t
6
OUT00 (D0)OUT07 (D3)OUT07 (D4)
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURING LOW LEVEL
LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE
UPDATE
0
6523-002
Figure 2. Timing Diagram, Serial Mode
Table 3. Logic Levels
Pins V
IH
V
IL
V
OH
V
OL
I
IH
I
IL
I
OH
I
OL
RESET, SER/PAR,
CLK, DATA IN,
CE,
UPDATE
2.0 V min 0.8 V max 20 μA max −400 μA min
DATA OUT 2.7 V min 0.5 V max −400 μA max 3.0 mA min