Datasheet

AD8112
Rev. 0 | Page 14 of 28
CAPACITIVE LOAD (pF)
300
250
200
150
100
50
0
SERIES RESISTANCE ()
V
S
=±12V
R
L
= 600
V
S
=±5V
R
L
= 150
0 5 10 15 20 25 30 35
06523-019
Figure 24. Capacitive Load vs. Series Resistance for Less than 30% Overshoot
IMPEDANCE ()
1
100
1k
10k
10
FREQUENCY (MHz)
0.1 1 10 100 1k
06523-020
Figure 25. Disabled Output Impedance vs. Frequency, V
S
= ±5 V
IMPEDANCE ()
1
100
1k
10
FREQUENCY (MHz)
0.1
0.1 1 10 100 1k
06523-021
Figure 26. Enabled Output Impedance vs. Frequency, V
S
= ±5 V
INPUT
OUTPUT
5ns/DIV
0.1%/DI
V
OUTPUT
– INPUT
2
0 5 10 15 20 25 30 35 40 45 50
06523-022
Figure 27. Settling Time to 0.1%, 2 V Step, V
S
= ±5 V, R
L
= 150 Ω
IMPEDANCE ()
1
100
1k
10k
10
FREQUENCY (MHz)
100 1k0.1 1 10
06523-053
Figure 28. Disabled Output Impedance vs. Frequency, V
S
= ±12 V
1
100
1k
10
FREQUENCY (MHz)
0.1
IMPEDANCE ()
0.1 1 10 100 1k
06523-054
Figure 29. Enabled Output Impedance vs. Frequency, V
S
= ±12 V