Datasheet

ManualsBrandsANALOG DEVICES ManualsInterface ICsInterface IC - analogue switches LQFP 80

REV. A

AD8110/AD8111

–6–

Table III. Operation Truth Table

SER/

CE UPDATE CLK DATA IN DATA OUT RESET PAR Operation/Comment

1 X X X X X X No change in logic.

01 f Data

Data

i-40

1 0 The data on the serial DATA IN line is loaded

into serial register. The first bit clocked into

the serial register appears at DATA OUT 40

clocks later.

01 f D0 . . . D4, NA in Parallel 1 1 The data on the parallel data lines, D0–D4, are

A0...A2 Mode loaded into the 40-bit serial shift register loca-

tion addressed by A0–A2.

0 0 X X X 1 X Data in the 40-bit shift register transfers into the

parallel latches that control the switch array.

Latches are transparent.

X X X X X 0 X Asynchronous operation. All outputs are disabled.

Remainder of logic is unchanged.

CLK

3 TO 8 DECODER

CLK

UPDATE

128

DATA IN

(SERIAL)

(OUTPUT

ENABLE)

SER/PAR

RESET

(OUTPUT ENABLE)

OUT0 EN

DATA

OUT

PARALLEL

DATA

CLK

OUT1 EN

OUT2 EN

OUT3 EN

OUT4 EN

OUT5 EN

OUT6 EN

OUT7 EN

QCLR

OUT7

OUTPUT ENABLE

SWITCH MATRIX

CLK

DECODE

QCLR

OUT0

OUT1

QCLR

OUT6

OUT7

CLK

OUT7

Figure 4. Logic Diagram