Datasheet

REV. A
AD8110/AD8111
–4–
TIMING CHARACTERISTICS (Parallel)
Limit
Parameter Symbol Min Max Unit
Data Setup Time t
1
20 ns
CLK Pulsewidth t
2
100 ns
Data Hold Time t
3
20 ns
CLK Pulse Separation t
4
100 ns
CLK to UPDATE Delay t
5
0ns
UPDATE Pulsewidth t
6
50 ns
Propagation Delay, UPDATE to Switch On or Off – 8 ns
CLK, UPDATE Rise and Fall Times – 100 ns
RESET Time – 200 ns
t
5
t
6
t
4
t
2
t
1
t
3
1
0
1
0
1 = LATCHED
CLK
D0–D4
A0–A2
0 = TRANSPARENT
UPDATE
Figure 2. Timing Diagram, Parallel Mode
Table II. Logic Levels
V
IH
V
IL
V
OH
V
OL
I
IH
I
IL
I
OH
I
OL
RESET, SER/PAR RESET, SER/PAR RESET, SER/PAR RESET, SER/PAR
CLK, D0, D1, D2, CLK, D0, D1, D2, CLK, D0, D1, D2, CLK, D0, D1, D2,
D3, D4, A0, A1, A2 D3, D4, A0, A1, A2 D3, D4, A0, A1, A2 D3, D4, A0, A1, A2
CE, UPDATE CE, UPDATE DATA OUT DATA OUT CE, UPDATE CE, UPDATE DATA OUT DATA OUT
2.0 V min 0.8 V max 2.7 V min 0.5 V max 20 µA max –400 µA min –400 µA max 3.0 mA min