Datasheet
REV. A
AD8110/AD8111
–3–
TIMING CHARACTERISTICS (Serial)
Limit
Parameter Symbol Min Typ Max Unit
Serial Data Setup Time t
1
20 ns
CLK Pulsewidth t
2
100 ns
Serial Data Hold Time t
3
20 ns
CLK Pulse Separation, Serial Mode t
4
100 ns
CLK to UPDATE Delay t
5
0ns
UPDATE Pulsewidth t
6
50 ns
CLK to DATA OUT Valid, Serial Mode t
7
180 ns
Propagation Delay, UPDATE to Switch On or Off – 8 ns
Data Load Time, CLK = 5 MHz, Serial Mode – 8 µs
CLK, UPDATE Rise and Fall Times – 100 ns
RESET Time – 200 ns
1
0
1
0
1 = LATCHED
0 = TRANSPARENT
DATA OUT
CLK
DATA IN
OUT7 (D4) OUT7 (D3) OUT00 (D0)
LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURING LOW LEVEL
t
2
t
4
t
1
t
3
t
7
t
5
t
6
UPDATE
Figure 1. Timing Diagram, Serial Mode
Table I. Logic Levels
V
IH
V
IL
V
OH
V
OL
I
IH
I
IL
I
OH
I
OL
RESET, SER/PAR RESET, SER/PAR RESET, SER/PAR RESET, SER/PAR
CLK, DATA IN, CLK, DATA IN, CLK, DATA IN, CLK, DATA IN,
CE, UPDATE CE, UPDATE DATA OUT DATA OUT CE, UPDATE CE, UPDATE DATA OUT DATA OUT
2.0 V min 0.8 V max 2.7 V min 0.5 V max 20 µA max –400 µA min –400 µA max 3.0 mA min