Datasheet

AD8106/AD8107
Rev. 0 | Page 7 of 28
Table 5. Operation Truth Table
CE UPDATE
CLK DATA IN DATA OUT
RESET
Operation/Comment
1 X X X X X No change in logic.
0 1 1
f
D0 … D4
A0 … A2
NA in parallel
mode
The data on the parallel data lines, D0 to D4, are loaded into
the 40-bit serial shift register location addressed by A0 to A2.
0 0 X X X 1
Data in the 40-bit shift register transfers into the parallel
latches that control the switch array. Latches are transparent.
X X X X X 0
Asynchronous operation. All outputs are disabled.
Remainder of logic is unchanged.
D
CLK
Q
3 TO 5 DECODER
A0
A1
A2
CLK
CE
UPDATE
5
80
(OUTPUT
ENABLE)
PARALLEL
DATA
D1
D2
D3
OUTPUT ENABLE
SWITCH MATRIX
D0
D4
05774-004
DLE
OUT0
B0
Q
D
CLK
Q
DLE
OUT0
B1
Q
D
CLK
Q
DLE
OUT0
B2
Q
D
CLK
Q
DLE
OUT0
B3
Q
D
CLK
Q
DLE
OUT1
B0
Q
D
CLK
Q
DLE
OUT3
EN
QCLR
D
CLK
Q
DLE
OUT4
B0
Q
D
CLK
Q
DLE
OUT4
B1
Q
D
CLK
Q
DLE
OUT4
B2
Q
D
CLK
Q
DLE
OUT4
B3
Q
OUT0 EN
OUT1 EN
OUT2 EN
OUT3 EN
OUT4 EN
RESET
(OUTPUT DISABLE)
D
CLK
Q
DLE
OUT0
EN
QCLR
D
CLK
Q
DLE
OUT4
EN
CLR
DECODE
Q
Figure 4. Logic Diagram