Datasheet

AD8104/AD8105
Rev. 0 | Page 5 of 36
TIMING CHARACTERISTICS (SERIAL MODE)
Specifications subject to change without notice.
Table 2.
Limit
Parameter Symbol Min Typ Max Unit
Serial Data Setup Time t
1
40 ns
CLK Pulse Width
t
2
50 ns
Serial Data Hold Time t
3
50 ns
CLK Pulse Separation
t
4
150 ns
CLK to UPDATE Delay
t
5
10 ns
UPDATE Pulse Width
t
6
90 ns
CLK to DATA OUT Valid
t
7
120 ns
Propagation Delay, UPDATE to Switch On or Off
100 ns
RESET Pulse Width
60 ns
RESET Time
200 ns
LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE
t
2
t
4
1
0
CLK
1
0
1
0
DATA IN
OUT15 (D5)
t
1
t
3
OUT15 (D4) OUT0 (D0)
1 = LATCHED
0 = TRANSPARENT
UPDATE
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURING LOW LEVEL
t
5
t
7
DATA OUT
t
6
WE
1
0
06612-002
Figure 2. Timing Diagram, Serial Mode
Table 3. Logic Levels
V
IH
V
IL
V
OH
V
OL
I
IH
I
IL
I
OH
I
OL
RESET,
SER
/PAR, CLK,
DATA IN,
UPDATE
RESET
,
SER
/PAR, CLK,
DATA IN,
UPDATE
DATA OUT DATA OUT
RESET
1
,
SER
/PAR, CLK,
DATA IN, UPDATE
RESET
1
,
SER
/PAR, CLK,
DATA IN, UPDATE
DATA OUT DATA OUT
2.0 V min 0.6 V max
VDD − 0.3 V
min
DGND +
0.5 V max
1 μA max –1 μA min −1 mA max 1 mA min
1
See Figure 15.