Datasheet

AD8104/AD8105
Rev. 0 | Page 27 of 36
however, until the
UPDATE
signal is taken low. It is thus possible
to latch in new data for several or all of the outputs first via
successive negative transitions of
WE
while
UPDATE
is held
high, and then have all the new data take effect when
UPDATE
goes low. This technique should be used when programming
the device for the first time after power-up when using parallel
programming.
Reset
When powering up the AD8104/AD8105, it is usually desirable
to have the outputs come up in the disabled state. The
RESET
pin, when taken low, causes all outputs to be in the disabled state.
However, the
UPDATE
signal does not reset all registers in the
AD8104/AD8105. This is important when operating in the
parallel programming mode. Refer to the
Parallel Programming
Description
section for information about programming internal
registers after power-up. Serial programming programs the entire
matrix each time; therefore, no special considerations apply.
Since the data in the shift register is random after power-up, it
should not be used to program the matrix, or the matrix can
enter unknown states. To prevent this, do not apply a logic low
signal to
UPDATE
initially after power-up. The shift register
should first be loaded with the desired data, and then
UPDATE
can be taken low to program the device.
The
RESET
pin has a 20 k pull-up resistor to VDD that can be
used to create a simple power-up reset circuit. A capacitor from
RESET
to ground holds
RESET
low for some time while the rest
of the device stabilizes. The low condition causes all the outputs
to be disabled. The capacitor then charges through the pull-up
resistor to the high state, thus allowing full programming
capability of the device.
Because the AD8104/AD8105 have random data in the internal
registers at power-up, the device may power up in a test state
where the supply current is larger than typical. Therefore, the
RESET
pin should be used to disable all outputs and bring the
device out of any test mode.
OPERATING MODES
The AD8104/AD8105 has fully differential inputs and outputs.
The inputs and outputs can also be operated in a single-ended
fashion. This presents several options for circuit configurations
that require different gains and treatment of terminations, if
they are used.
Differential Input
Each differential input to the AD8104/AD8105 is applied to a
differential receiver. These receivers allow the user to drive the
inputs with a differential signal with an uncertain common-
mode voltage, such as from a remote source over twisted pair.
The receivers respond only to the difference in input voltages,
and will restore a common-mode voltage suitable for the
internal signal path. Noise or crosstalk that is present in both
inputs is rejected by the input stage, as specified by its common-
mode rejection ratio (CMRR). Differential operation offers a
great noise benefit for signals that are propagated over distance
in a noisy environment.
IN+
VOCM
IN–
R
G
R
G
RCVR
R
F
R
F
OUT–
OUT+
TO SWITCH MATRIX
06612-065
Figure 65. Input Receiver Equivalent Circuit
The circuit configuration used by the differential input receivers
is similar to that of several Analog Devices, Inc. general-purpose
differential amplifiers, such as the
AD8131. It is a voltage
feedback amplifier with internal gain setting resistors. The
arrangement of feedback makes the differential input imped-
ance appear to be 5 k across the inputs.
k52
,
=
×
=
G
dmIN
RR
This impedance creates a small differential termination error if
the user does not account for the 5 k parallel element, although
this error is less than 1% in most cases. Additionally, the source
impedance driving the AD8104/AD8105 appears in parallel
with the internal gain-setting resistors, such that there may be a
gain error for some values of source resistance. The AD8104/
AD8105 are adjusted such that its gains are correct when driven
by a back-terminated 75  source impedance at each input
phase (37.5  effective impedance to ground at each input pin,
or 75  differential source impedance across pairs of input
pins). If a different source impedance is presented, the differential
gain of the AD8104/AD8105 can be calculated by
SG
F
dmIN
OUT,dm
dm
RR
R
V
V
G
+
==
,
where:
R
G
= 2.5 k.
R
S
is the user single-ended source resistance (such as 37.5  for
a back-terminated 75  source).
R
F
= 2.538 k for the AD8104 and 5.075 k for the AD8105.
In the case of the AD8104,
S
dm
R
G
+
=
k5.2
k538.2
In the case of the AD8105,
S
dm
R
G
+
=
k5.2
k075.5