Datasheet

AD8104/AD8105
Rev. 0 | Page 25 of 36
THEORY OF OPERATION
The AD8104/AD8105 are fully differential crosspoint arrays
with 16 outputs, each of which can be connected to any one
of 32 inputs. Organized by output row, 32 switchable input
transconductance stages are connected to each output buffer to
form 32-to-1 multiplexers. There are 16 of these multiplexers,
each with its inputs wired in parallel, for a total array of 512
transconductance stages forming a multicast-capable crosspoint
switch.
Decoding logic for each output selects one (or none) of the
transconductance stages to drive the output stage. The enabled
transconductance stage drives the output stage, and feedback
forms a closed-loop amplifier with a differential gain of +1 (the
difference between the output voltages is equal to the difference
between the input voltages). A second feedback loop controls
the common-mode output level, forcing the average of the
differential output voltages to match the voltage on the VOCM
reference pin. Although each output has an independent
common-mode control loop, the VOCM reference is common
for the entire chip, and as such needs to be driven with a low
impedance to avoid crosstalk.
Each differential input to the AD8104/AD8105 is buffered by a
receiver. The purpose of this receiver is to provide an extended
input common-mode range, and to remove this common mode
from the signal chain. Like the output multiplexers, the input
receiver has both a differential loop and a common-mode
control loop. A mask-programmable feedback network sets the
closed-loop differential gain. For the AD8104, this differential
gain is +1, and for the AD8105, this differential gain is +2. The
receiver has an input stage that does not respond to the
common mode of the signal. This architecture, along with the
attenuating feedback network, allows the user to apply input
voltages that extend from rail to rail. Excess differential loop
gain bandwidth product reduces the effect of the closed-loop
gain on the bandwidth of the device.
The output stage of the AD8104/AD8105 is designed for low
differential gain and phase error when driving composite video
signals. It also provides slew current for fast pulse response
when driving component video signals. Unlike many multi-
plexer designs, these requirements are balanced such that large
signal bandwidth is very similar to small signal bandwidth. The
design load is 150 , but provisions are made to drive loads
as low as 75  as long as on-chip power dissipation limits are
not exceeded.
The outputs of the AD8104/AD8105 can be disabled to
minimize on-chip power dissipation. When disabled, there is a
feedback network of 25 k between the differential outputs.
This high impedance allows multiple ICs to be bussed together
without additional buffering. Care must be taken to reduce
output capacitance, which results in more overshoot and
frequency domain peaking. A series of internal amplifiers drive
internal nodes such that a wideband high impedance is
presented at the disabled output, even while the output bus is
under large signal swings. When the outputs are disabled and
driven externally, the voltage applied to them should not exceed
the valid output swing range for the AD8104/AD8105 in order
to keep these internal amplifiers in their linear range of
operation. Applying excess differential voltages to the disabled
outputs can cause damage to the AD8104/AD8105 and should
be avoided (see the
Absolute Maximum Ratings section for
guidelines).
The connection of the AD8104/AD8105 is controlled by a
flexible TTL-compatible logic interface. Either parallel or serial
loading into a first rank of latches preprograms each output. A
global update signal moves the programming data into the
second rank of latches, simultaneously updating all outputs. In
serial mode, a serial-out pin allows devices to be daisy-chained
together for single-pin programming of multiple ICs. A power-
on reset pin is available to avoid bus conflicts by disabling all
outputs. This power-on reset clears the second rank of latches,
but does not clear the first rank of latches. In parallel mode, to
quickly clear the first rank, a broadcast parallel programming
feature is available. In serial mode, preprogramming individual
inputs is not possible and the entire shift register needs to
be flushed.
The AD8104/AD8105 can operate on a single +5 V supply,
powering both the signal path (with the VPOS/VNEG supply
pins), and the control logic interface (with the VDD/DGND
supply pins). However, to easily interface to ground-referenced
video signals, split supply operation is possible with ±2.5 V
supplies. In this case, a flexible logic interface allows the control
logic supplies (VDD/DGND) to be run off +2 V/0 V to
+5 V/0 V while the core remains on split supplies. Additional
flexibility in the analog output common-mode level facilitates
unequal split supplies. If +3 V/–2 V supplies to +2 V/–3 V
supplies are desired, the VOCM pin can still be set to 0 V for
ground-referenced video signals.