Datasheet

AD8104/AD8105
Rev. 0 | Page 16 of 36
V
POS
VNEG
IPn, INn,
OPn, ONn,
VOCM
V
DD
DGND
CLK, RESET,
SER/PAR, WE,
UPDATE,
DATA IN,
DATA OUT,
A[3:0], D[5:0]
06612-018
CLK, SER/PAR, WE,
UPDATE, DATA IN,
A[3:0], D[5:0]
DGND
1kΩ
0
6612-016
Figure 16. Logic Input (see also ESD Protection Map,
Figure 18)
Figure 18. ESD Protection Map
V
DD
DGND
DATA OUT
0
6612-017
Figure 17. Logic Output (see also ESD Protection Map,
Figure 18)