Datasheet

AD8104/AD8105
Rev. 0 | Page 15 of 36
I/O SCHEMATICS
OPn, ONn
06612-008
Figure 8. AD8104/AD8105 Enabled Output
(see also ESD Protection Map,
Figure 18)
0.4pF 30kΩ
3.4pF
3.4pF
OPn
ONn
06612-009
Figure 9. AD8104/AD8105 Disabled Output
(see also ESD Protection Map,
Figure 18)
1.3pF
1.3pF
0.3pF
IPn
INn
2500Ω
2500Ω
2538Ω
2538Ω
06612-010
Figure 10. AD8104 Receiver (see also ESD Protection Map,
Figure 18)
2500
Ω
5075Ω
0.3pF
1.3pF
1.3pF
2500Ω 5075Ω
IPn
INn
0
6612-011
Figure 11. AD8105 Receiver (see also ESD Protection Map,
Figure 18)
1.3pF
1.3pF
0.3pF
IP
n
INn
2500Ω
2500Ω
0
6612-012
Figure 12. AD8104/AD8105 Receiver Simplified Equivalent Circuit When
Driving Differentially
1.6pF
IP
n
INn
3.33kΩ AD8104 G = +1
3.76kΩ AD8105 G = +2
0
6612-013
Figure 13. AD8104/AD8105 Receiver Simplified Equivalent Circuit When
Driving Single-Ended
V
OCM
VNEG
0
6612-014
Figure 14. VOCM Input (see also ESD Protection Map,
Figure 18)
RESET
DGND
V
DD
1kΩ
25kΩ
0
6612-015
Figure 15. Reset Input (see also ESD Protection Map,
Figure 18)