Datasheet

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600 MHz, 32 × 16 Buffered

Analog Crosspoint Switch

AD8104/AD8105

Rev. 0

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FEATURES

High channel count, 32 × 16 high speed, nonblocking

switch array

Differential or single-ended operation

Differential G = +1 (AD8104) or G = +2 (AD8105)

Pin compatible with

AD8117/AD8118, 32 × 32 switch arrays

Flexible power supplies

Single +5 V supply, or dual ±2.5 V supplies

Serial or parallel programming of switch array

High impedance output disable allows connection of

multiple devices with minimal loading on output bus

Excellent video performance

>50 MHz 0.1 dB gain flatness

0.05% differential gain error (R

= 150 Ω)

0.05° phase error (R

= 150 Ω)

Excellent ac performance

Bandwidth: 600 MHz

Slew rate: 1800 V/μs

Settling time: 2.5 ns to 1%

Low power of 1.7 W

Low all hostile crosstalk

< −70 dB @ 5 MHz

< −40 dB @ 600 MHz

Reset pin allows disabling of all outputs (connected through

a capacitor to ground provides power-on reset capability)

304-ball BGA package (31 mm × 31 mm)

APPLICATIONS

Routing of high speed signals including

RGB and component video routing

KVM

Compressed video (MPEG, wavelet)

Data communications

FUNCTIONAL BLOCK DIAGRAM

INPUT

RECEIVER

G = +1*

G = +2**

OUTPUT

BUFFER

G = +1

512

SET INDIVIDUAL, OR

RESET ALL OUTPUTS TO OFF

ENABLE/DISABLE

VPOS VNEG VOCM

32 INPUT PAIRS

RESET

UPDATE

CLK

DATA IN

SER/PAR

DATA

OUT

16 OUTPUT PAIRS

SWITCH

MATRIX

D0 D1 D2 D3 D4 D5 VDD DGND

AD8104/

AD8105

192-BIT SHIFT REGISTER

WITH 6-BIT

PARALLEL LOADING

PARALLEL LATCH

DECODE

16 × 6:32 DECODERS

*AD8104 ONLY

**AD8105 ONLY

06612-001

CONNECT

Figure 1.

GENERAL DESCRIPTION

The AD8104/AD8105 are high speed, 32 × 16 analog crosspoint

switch matrices. They offer 600 MHz bandwidth and slew rate of

1800 V/µs for high resolution computer graphics (RGB) signal

switching. With less than −70 dB of crosstalk and −90 dB isola-

tion (@ 5 MHz), the AD8104/AD8105 are useful in many high

speed applications. The 0.1 dB flatness, which is greater than

50 MHz, makes the AD8104/AD8105 ideal for composite video

switching.

The AD8104/AD8105 include 16 independent output buffers

that can be placed into a high impedance state for paralleling

crosspoint outputs so that off-channels present minimal loading

to an output bus. The AD8104 has a differential gain of +1,

while the AD8105 has a differential gain of +2 for ease of use

in back-terminated load applications. They operate as fully

differential devices or can be configured for single-ended

operation. Either a single +5 V supply or dual ±2.5 V supplies

can be used, while consuming only 340 mA of idle current with

all outputs enabled. The channel switching is performed via a

double-buffered, serial digital control (which can accommodate

daisy-chaining of several devices), or via a parallel control,

allowing updating of an individual output without reprogram-

ming the entire array.

The AD8104/AD8105 are packaged in a 304-ball BGA package

and are available over the extended industrial temperature

range of −40°C to +85°C.

Summary of content (36 pages)

PAGE 1
600 MHz, 32 × 16 Buffered Analog Crosspoint Switch AD8104/AD8105 APPLICATIONS Routing of high speed signals including RGB and component video routing KVM Compressed video (MPEG, wavelet) Data communications GENERAL DESCRIPTION The AD8104/AD8105 are high speed, 32 × 16 analog crosspoint switch matrices. They offer 600 MHz bandwidth and slew rate of 1800 V/μs for high resolution computer graphics (RGB) signal switching.
PAGE 2
AD8104/AD8105 TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................7 Applications....................................................................................... 1 Pin Configuration and Function Descriptions..............................8 Functional Block Diagram ..............................................................
PAGE 3
AD8104/AD8105 SPECIFICATIONS VS = ±2.5 V at TA = 25°C, RL, diff = 200 Ω, VOCM = 0 V, differential I/O mode, unless otherwise noted. Table 1.
PAGE 4
AD8104/AD8105 Parameter SWITCHING CHARACTERISTICS Enable On Time Switching Time, 2 V Step Switching Transient (Glitch) POWER SUPPLIES Supply Current Supply Voltage Range PSRR OPERATING TEMPERATURE RANGE Temperature Range θJA θJC Conditions Min AD8104/AD8105 Typ Max 50% update to 1% settling 50% update to 1% settling Differential 100 100 40 VPOS, outputs enabled, no load VPOS, outputs disabled VNEG, outputs enabled, no load VNEG, outputs disabled VDD, outputs enabled, no load 340 210 340 210 Unit ns
PAGE 5
AD8104/AD8105 TIMING CHARACTERISTICS (SERIAL MODE) Specifications subject to change without notice. Table 2.
PAGE 6
AD8104/AD8105 TIMING CHARACTERISTICS (PARALLEL MODE) Specifications subject to change without notice. Table 4.
PAGE 7
AD8104/AD8105 ABSOLUTE MAXIMUM RATINGS POWER DISSIPATION Table 6. Rating 6V The AD8104/AD8105 are operated with ±2.5 V or +5 V supplies and can drive loads down to 100 Ω, resulting in a large range of possible power dissipations. For this reason, extra care must be taken derating the operating conditions based on ambient temperature. 6V +0.5 V to −2.
PAGE 8
AD8104/AD8105 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A VPOS VPOS VPOS VPOS NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VPOS VPOS VPOS A B VPOS VPOS VPOS NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VPOS VPOS VPOS VPOS B C VPOS VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VPOS C D IN16 VPOS VPOS VNEG VOCM VNEG VNEG V
PAGE 9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 A VPOS VPOS VPOS NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VPOS VPOS VPOS VPOS A B VPOS VPOS VPOS VPOS NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VPOS VPOS VPOS B C VPOS VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VPOS C D VPOS IP0 VPOS VNEG VOCM VNEG VNEG VNEG VNEG VNEG
PAGE 10
AD8104/AD8105 Ball No. B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 D1 D2 D3 D4 D5 Mnemonic NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VPOS VPOS VPOS VPOS VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VPOS VPOS IP0 VPOS VNEG VOCM D6 D7 D8 D9 D10 D11 VNEG VNEG VNEG VNEG VNEG VPOS Description No Connect. No Connect. No Connect. No Connect.
PAGE 11
AD8104/AD8105 Ball No. J21 J22 J23 K1 K2 K3 K4 K20 K21 K22 K23 L1 L2 L3 L4 L20 L21 L22 L23 M1 M2 M3 M4 M20 M21 M22 M23 N1 N2 N3 N4 N20 N21 N22 N23 P1 P2 P3 P4 P20 P21 P22 P23 R1 R2 R3 R4 R20 R21 R22 R23 T1 Mnemonic VNEG IN21 IP20 IN5 IP6 VNEG DATA IN WE VNEG IP21 IN22 IP7 IN6 VPOS SER/PAR D5 VPOS IN23 IP22 IN7 IP8 VPOS DGND D4 VPOS IP23 IN24 IP9 IN8 VPOS A3 D3 VPOS IN25 IP24 IN9 IP10 VNEG A2 D2 VNEG IP25 IN26 IP11 IN10 VNEG A1 D1 VNEG IN27 IP26 IN11 Description Analog Negative Power Supply.
PAGE 12
AD8104/AD8105 Ball No. Y19 Mnemonic VOCM Y20 Y21 Y22 Y23 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 VNEG VPOS IP31 VPOS VPOS VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VNEG VNEG VNEG VNEG VNEG VNEG VPOS VPOS VPOS VPOS VPOS VPOS VPOS OP0 ON0 OP2 ON2 OP4 ON4 Description Output Common-Mode Reference Supply. Analog Negative Power Supply. Analog Positive Power Supply.
PAGE 13
AD8104/AD8105 TRUTH TABLE AND LOGIC DIAGRAM Table 9. Operation Truth Table DATA INPUT X DATA OUTPUT X RESET 0 X Datai 1 Datai-192 1 0 X D0…D5 2 A0…A3 3 1 1 0 X X 1 X X X X N/A in parallel mode N/A in parallel mode X 1 1 WE X UPDATE X 1 X 0 X 1 1 CLK X 1 Datai: serial data. D0…D5: data bits. 3 A0…A3: address bits. 2 Rev. 0 | Page 13 of 36 SER/PAR Operation/Comment Asynchronous reset. All outputs are disabled. Remainder of logic in 192-bit shift register is unchanged.
PAGE 14
OUTPUT ADDRESS A0 A1 A2 A3 4 TO 16 DECODER CLK WE DATA IN (SERIAL) Figure 7. Logic Diagram Rev.
PAGE 15
AD8104/AD8105 I/O SCHEMATICS IPn 1.3pF 2500Ω 1.3pF 2500Ω 06612-008 INn 06612-012 0.3pF OPn, ONn Figure 12. AD8104/AD8105 Receiver Simplified Equivalent Circuit When Driving Differentially Figure 8. AD8104/AD8105 Enabled Output (see also ESD Protection Map, Figure 18) OPn IPn 3.4pF 3.33kΩ AD8104 G = +1 3.76kΩ AD8105 G = +2 1.6pF 30kΩ 06612-013 0.4pF INn 3.4pF 06612-009 ONn Figure 13. AD8104/AD8105 Receiver Simplified Equivalent Circuit When Driving Single-Ended Figure 9.
PAGE 16
AD8104/AD8105 VPOS 1kΩ DGND VNEG VDD 06612-017 DATA OUT DGND DGND Figure 18. ESD Protection Map Figure 16. Logic Input (see also ESD Protection Map, Figure 18) Figure 17. Logic Output (see also ESD Protection Map, Figure 18) Rev.
PAGE 17
AD8104/AD8105 TYPICAL PERFORMANCE CHARACTERISTICS VS = ±2.5 V at TA = 25°C, RL, diff = 200 Ω, VOCM = 0 V, differential I/O mode, unless otherwise noted. 200 10 180 AD8105 6 160 4 140 120 AD8104 0 100 –2 80 –4 60 –6 40 –8 –10 1 100 10 06612-022 COUNT 2 06612-019 GAIN (dB) 8 20 0 1000 540 560 580 FREQUENCY (MHz) 640 660 700 800 AD8105 6 4 2 AD8104 0 –2 –4 06612-020 –6 –8 1 10 –1.0 –1.5 –2.0 1000 100 –0.
PAGE 18
AD8104/AD8105 0 –15 DIFFERENTIAL OUT DIFFERENTIAL IN/OUT VNEG AGGRESSOR –25 –20 –35 CROSSTALK (dB) VPOS AGGRESSOR PSR (dB) –45 –55 VOCM AGGRESSOR –65 –40 –60 –75 06612-025 –95 0.1 1 10 100 –100 300k 1000 06612-028 –80 –85 1M Figure 25.
PAGE 19
AD8104/AD8105 0 0 SINGLE-ENDED IN/OUT –20 CROSSTALK (dB) –20 –40 –60 –80 –40 –60 –80 –100 300k 06612-031 –100 1M 10M 100M –120 300k 1G 06612-034 CROSSTALK (dB) SINGLE-ENDED IN/OUT 1M Figure 31. AD8105 Crosstalk, One Adjacent Channel, Single-Ended 0 SINGLE-ENDED IN/OUT –20 –40 CROSSTALK (dB) CROSSTALK (dB) –20 –60 –80 –40 –60 –80 06612-032 –100 1M 10M 100M –100 300k 1G 1M FREQUENCY (Hz) 0 100M 1G Figure 35.
PAGE 20
AD8104/AD8105 0 30000 SINGLE-ENDED IN/OUT 25000 OUTPUT IMPEDANCE (Ω) –40 –60 –80 20000 15000 10000 06612-037 5000 1M 10M 100M 1G 06612-040 FEEDTHROUGH (dB) –20 –100 300k DIFFERENTIAL OUT 0 100k 2G 1M 10M FREQUENCY (Hz) Figure 37. AD8104 Crosstalk, Off Isolation, Single-Ended 6000 100M 1G FREQUENCY (Hz) Figure 40.
PAGE 21
AD8104/AD8105 3 1.5 0.20 UPDATE 0.15 1.0 2 0.5 1 0 0 0 –0.05 P-CHANNEL –1.0 –0.20 06612-043 –0.15 0 1 2 3 4 5 6 7 8 9 –1 –0.5 –0.10 VOUT –1.5 –40 10 11 12 13 14 15 –2 –20 0 20 40 60 80 100 –3 120 06612-046 VOUT (V, DIFF) VOUT (V, SE) N-CHANNEL 0.05 UPDATE (V) 0.10 TIME (ns) TIME (ns) Figure 46. AD8104 Switching Time Figure 43. AD8104 Small Signal Pulse Response, Single-Ended, 200 mV p-p 2.0 1.5 2 5000 1 4000 0 3000 0.5 0 –0.
PAGE 22
AD8104/AD8105 0.014 5 DIFFERENTIAL PHASE ERROR (%) 0.012 3 2 1 0 10 20 30 40 50 60 70 80 0.008 0.006 0.004 0.002 0 –0.002 06612-049 0 –40 –30 –20 –10 0.010 –0.004 –700 90 100 06612-052 OFFSET (mV) 4 –500 –300 –100 100 300 500 700 VIN, DIFF (mV) TEMPERATURE (ºC) Figure 49. AD8104 VOS vs. Temperature with All Outputs Enabled Figure 52. AD8104 Phase vs. DC Voltage, Carrier Frequency = 3.58 MHz, Subcarrier Amplitude = 600 mV p-p, Differential 50 2.0 40 1.5 10pF 5pF 1.
PAGE 23
AD8104/AD8105 2.8 IDD (SERIAL MODE) 0.8 1.6 0.6 1.2 0.4 0.8 0.4 VOUT IPOS AND INEG CURRENT (mA) 2.0 UPDATE (V) 2.4 1.0 0.2 500 750 IDD (PARALLEL MODE) 400 –0.2 –50 –30 –10 10 30 50 70 90 110 130 –0.4 150 TIME (ns) 650 IPOS AND INEG (ALL OUTPUTS ENABLED) 300 200 550 450 IPOS AND INEG (ALL OUTPUTS DISABLED) 0 0 100 –35 –25 –15 –5 5 15 25 35 45 55 65 75 85 350 95 TEMPERATURE (°C) Figure 55. AD8104 Enable Time Figure 58.
PAGE 24
AD8104/AD8105 5 2.0 4 1.5 VOUTP 1.0 2 1 VOUT (V, SE) 0 –1 0.5 VINP 0 –0.5 –2 –1.0 –3 –1.5 06612-061 –4 –5 0 1 2 3 4 5 6 VOUTN VINN 06612-063 OUTPUT/INPUT (%) 3 –2.0 7 100 0 200 300 TIME (ns) Figure 61. AD8104 Settling Time (Zoom) –30 VINP 700 VOUT = 2V p-p, DIFF –50 DISTORTION (dBc) 1.0 0.5 0 –0.5 –1.0 THIRD HARMONIC –60 –70 SECOND HARMONIC –80 VOUTN –2.0 VINN –2.5 0 100 200 300 400 500 –90 600 –100 0.1 700 TIME (ns) 06612-064 –1.
PAGE 25
AD8104/AD8105 THEORY OF OPERATION The AD8104/AD8105 are fully differential crosspoint arrays with 16 outputs, each of which can be connected to any one of 32 inputs. Organized by output row, 32 switchable input transconductance stages are connected to each output buffer to form 32-to-1 multiplexers. There are 16 of these multiplexers, each with its inputs wired in parallel, for a total array of 512 transconductance stages forming a multicast-capable crosspoint switch.
PAGE 26
AD8104/AD8105 APPLICATIONS INFORMATION PROGRAMMING The AD8104/AD8105 have two options for changing the programming of the crosspoint matrix. In the first option, a serial word of 192 bits can be provided to update the entire matrix each time. The second option allows for changing the programming of a single output via a parallel interface.
PAGE 27
AD8104/AD8105 mode rejection ratio (CMRR). Differential operation offers a great noise benefit for signals that are propagated over distance in a noisy environment. RF RG IN+ OUT– RCVR VOCM IN– Reset OUT+ RG When powering up the AD8104/AD8105, it is usually desirable to have the outputs come up in the disabled state. The RESET pin, when taken low, causes all outputs to be in the disabled state. However, the UPDATE signal does not reset all registers in the AD8104/AD8105.
PAGE 28
AD8104/AD8105 When operating with a differential input, care must be taken to keep the common mode, or average, of the input voltages within the linear operating range of the AD8104/AD8105 receiver. This common-mode range can extend rail-to-rail, provided the differential signal swing is small enough to avoid forward biasing the ESD diodes (it is safest to keep the common mode plus differential signal excursions within the supply voltages of the part).
PAGE 29
AD8104/AD8105 Differential Gain The specified signal path gain of the AD8104/AD8105 refers to its differential gain. For the AD8104, the gain of +1 means that the difference in voltage between the two output terminals is equal to the difference applied between the two input terminals. For the AD8105, the ratio of output difference voltage to applied input difference voltage is +2.
PAGE 30
AD8104/AD8105 Single-Ended Gain The AD8104/AD8105 operate as a closed-loop differential amplifier. The primary control loop forces the difference between the output terminals to be a ratio of the difference between the input terminals. One output increases in voltage, while the other decreases an equal amount to make the total difference correct. The average of these output voltages is forced to be equal to the voltage on the VOCM terminal by a second control loop.
PAGE 31
AD8104/AD8105 VPOS operation as well, as there is a common-mode-to-differential gain conversion that becomes greater at higher frequencies. IOUTPUT, QUIESCENT During operation of the AD8104/AD8105, transient currents flow into the VOCM net from the amplifier control loops. Although the magnitude of these currents are small (10 μA to 20 μA per output), they can contribute to crosstalk if they flow through significant impedances. Driving VOCM with a low impedance, low noise source is desirable.
PAGE 32
AD8104/AD8105 Short-Circuit Output Conditions Although there is short-circuit current protection on the AD8104/AD8105 outputs, the output current can reach values of 80 mA into a grounded output. Any sustained operation with too many shorted outputs can exceed the maximum die temperature and can result in device failure (see the Absolute Maximum Ratings section).
PAGE 33
AD8104/AD8105 there is only one way to drive a test signal into all 31 other inputs in parallel. Each of these cases is legitimately different from the others and may yield a unique value, depending on the resolution of the measurement system, but it is hardly practical to measure all these terms and then specify them. In addition, this describes the crosstalk matrix for just one input channel. A similar crosstalk matrix can be proposed for every other input.
PAGE 34
AD8104/AD8105 From a circuit standpoint, this output crosstalk mechanism looks like a transformer with a mutual inductance between the windings that drive a load resistor. For low frequencies, the magnitude of the crosstalk is given by ⎛ s ⎞⎟ XT = 20 log 10 ⎜ M XY × ⎜ RL ⎟⎠ ⎝ where: MXY is the mutual inductance of Output X to Output Y. RL is the load resistance on the measured output. This crosstalk mechanism can be minimized by keeping the mutual inductance low and increasing RL.
PAGE 35
AD8104/AD8105 If multiple AD8104/AD8105s are to be driven in parallel, a flyby input termination scheme is very useful, but the distance from each AD8104/AD8105 input to the driven input transmission line is a stub that should be minimized in length and parasitics using the discussed guidelines. system). This is not often practical as trace widths become large. In most cases, the best practical solution is to place the halfcharacteristic impedance resistor as close as possible (preferably less than 1.
PAGE 36
AD8104/AD8105 OUTLINE DIMENSIONS A1 CORNER INDEX AREA 31.00 BSC SQ 23 6 4 2 22 20 18 16 14 12 10 8 21 19 17 15 13 11 9 5 3 7 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC BALL A1 INDICATOR 27.94 BSC SQ TOP VIEW BOTTOM VIEW 1.27 BSC DETAIL A DETAIL A *1.765 MAX 1.07 0.99 0.92 0.70 0.63 0.56 0.10 MIN COPLANARITY 0.20 SEATING PLANE *COMPLIANT TO JEDEC STANDARDS MO-192-BAN-2 WITH THE EXCEPTION TO PACKAGE HEIGHT. 022206-A 0.25 MIN (4 ) 0.90 0.75 0.60 BALL DIAMETER Figure 74.