Datasheet

Data Sheet AD8067
Rev. B | Page 15 of 24
DC ERROR CALCULATIONS
Figure 44 illustrates the primary dc errors associated with a
voltage feedback amplifier. For both inverting and noninverting
configurations:








+
=
G
F
G
OSOS
R
RR
VVtodueErrorVoltageOutput
FB–
G
G
F
S
BB
RI
R
RR
RIItodueErrorVoltageOutput ×








+
×=
+
–
Total error is the sum of the two.
DC common-mode and power supply effects can be added by
modeling the total V
OS
with the expression:
CMR
V
PSR
V
nomVtotV
CMS
OSOS
ΔΔ
)()( ++=
where:
V
OS
(nom) is the offset voltage specified at nominal conditions
(1 mV max).
∆V
S
is the change in power supply voltage from nominal
conditions.
PSR is power supply rejection (90 dB minimum).
∆V
CM
is the change in common-mode voltage from nominal test
conditions.
CMR is the common-mode rejection (85 dB minimum for the
AD8067).
V
I
R
S
R
G
I
B
+
I
B
–
–
+
V
OUT
–
+
–
+
+V
OS
–
R
F
Figure 44. Op Amp DC Error Sources
INPUT AND OUTPUT OVERLOAD BEHAVIOR
A simplified schematic of the AD8067 input stage is shown in
Figure 45. This shows the cascoded N-channel JFET input pair,
the ESD and other protection diodes, and the auxiliary NPN
input stage that eliminates phase inversion behavior.
When the common-mode input voltage to the amplifier is
driven to within approximately 3 V of the positive power
supply, the input JFET’s bias current turns off, and the bias of
the NPN pair turns on, taking over control of the amplifier. The
NPN differential pair now sets the amplifier’s offset, and the
input bias current is now in the range of several tens of
microamps. This behavior is illustrated in Figure 25 and Figure 26.
Normal operation resumes when the common-mode voltage
goes below the 3 V from the positive supply threshold.
The output transistors have circuitry included to limit the
extent of their saturation when the output is overdriven. This
improves output recovery time. A plot of the output recovery
time for the AD8067 used as a G = +10 buffer is shown in
Figure 17.
V
BIAS
V
CC
V
EE
V
EE
V
CC
V
P
V
N
SWITCH
CONTROL
V
EE
V
CC
TO REST OF AMP
V
THRESHOLD
Figure 45. Simplified Input Schematic