Datasheet

AD8065/AD8066
Rev. J | Page 21 of 28
The closed-loop bandwidth is inversely proportional to the noise
gain of the op amp circuit, (R
F
+ R
G
)/R
G
. This simple model is
accurate for noise gains above 2. The actual bandwidth of circuits
with noise gains at or below 2 is higher than those predicted
with this model due to the influence of other poles in the
frequency response of the real op amp.
V
O
R
F
A
R
G
V
I
I
b –
R
S
I
b +
+V
OS
–
02916-E-054
Figure 54. Voltage Feedback Amplifier DC Errors
Figure 54 shows a voltage feedback amplifier’s dc errors. For
both inverting and noninverting configurations
()
⎟
⎠
⎞
⎜
⎝
⎛
+
+×−
⎟
⎠
⎞
⎜
⎝
⎛
+
×=
−+
G
F
G
OS
F
b
G
F
G
S
b
O
R
RR
VRI
R
RR
RIerrorV
The voltage error due to I
b+
and I
b–
is minimized if R
S
= R
F
|| R
G
(though with the AD8065 input currents at typically less than
20 pA over temperature, this is likely not a concern). To include
common-mode and power supply rejection effects, total V
OS
can be
modeled
CMR
V
PSR
V
VV
CMS
nom
OSOS
ΔΔ
++=
nom
OS
V
is the offset voltage specified at nominal conditions,
ΔV
S
is the change in power supply from nominal conditions,
PSR is the power supply rejection, ΔV
CM
is the change in common-
mode voltage from nominal conditions, and CMR is the common-
mode rejection.
WIDEBAND OPERATION
Figure 42 through Figure 44 show the circuits used for wideband
characterization for gains of +1, +2, and −1. Source impedance at
the summing junction (R
F
|| R
G
) forms a pole in the amplifier’s loop
response with the amplifier’s input capacitance of 6.6 pF. This
can cause peaking and ringing if the time constant formed is too
low. Feedback resistances of 300 Ω to 1 kΩ are recommended,
because they do not unduly load down the amplifier, and the
time constant formed will not be too low. Peaking in the
frequency response can be compensated for with a small
capacitor (C
F
) in parallel with the feedback resistor, as
illustrated in Figure 12. This shows the effect of different
feedback capacitances on the peaking and bandwidth for a
noninverting G = +2 amplifier.
For the best settling times and the best distortion, the impedances
at the AD8065/AD8066 input terminals should be matched. This
minimizes nonlinear common-mode capacitive effects that can
degrade ac performance.
Actual distortion performance depends on a number of
variables:
• The closed-loop gain of the application
• Whether it is inverting or noninverting
• Amplifier loading
• Signal frequency and amplitude
• Board layout
Also see Figure 16 to Figure 20. The lowest distortion is obtained
with the AD8065 used in low gain inverting applications,
because this eliminates common-mode effects. Higher closed-
loop gains result in worse distortion performance.
INPUT PROTECTION
The inputs of the AD8065/AD8066 are protected with back-to-
back diodes between the input terminals as well as ESD diodes
to either power supply. This results in an input stage with picoamps
of input current that can withstand up to 1500 V ESD events
(human body model) with no degradation.
Excessive power dissipation through the protection devices
destroys or degrades the performance of the amplifier. Differ-
ential voltages greater than 0.7 V result in an input current of
approximately (|V
+
− V
−
| 0.7 V)/R
I
, where R
I
is the resistance in
series with the inputs.
For input voltages beyond the positive supply, the input current
is approximately (V
I
− V
CC
− 0.7)/R
I
. Beyond the negative supply,
the input current is about (V
I
− V
EE
+ 0.7)/R
I
. If the inputs of the
amplifier are to be subjected to sustained differential voltages
greater than 0.7 V, or to input voltages beyond the amplifier
power supply, input current should be limited to 30 mA by an
appropriately sized input resistor (R
I
), as shown in Figure 55.
R
I
V
I
V
O
AD8065
R
I
>
(| V
+
–V
–
| – 0.7V)
30mA
FOR LARGE | V
+
–V
–
|
R
I
>
(V
I
–V
EE
– 0.7V)
30mA
R
I
>
(V
I
–V
EE
+ 0.7V)
30mA
FOR V
I
BEYOND
SUPPLY VOLTAGES
02916-E-055
Figure 55. Current-Limiting Resistor