Datasheet

REV. C–14–
AD8011
LAYOUT CONSIDERATIONS
The specified high speed performance of the AD8011 requires
careful attention to board layout and component selection. Table I
shows the recommended component values for the AD8011.
Proper R
F
design techniques and low parasitic component selec-
tion are mandatory.
Table I. Typical Bandwidth vs. Gain Setting Resistors
Small Signal
–3 dB BW (MHz),
Gain R
F
(⍀)R
G
(⍀)R
T
(⍀)V
S
= ⴞ5 V
–1 1000 1000 52.3 150
–2 1000 499 54.9 130
–10 499 49.9 140
+1 1000 49.9 400
[phone] 49.9 250
+10 422 47.5 49.9 100
[phone] 49.9 70
+6 500 100 49.9 170
R
T
chosen for 50 Ω characteristic input impedance. R
O
chosen for characteristic
output impedance.
The PCB should have a ground plane covering all unused
portions of the component side of the board to provide a low
impedance ground path. The ground plane should be removed
from the area near the input pins to reduce stray capacitance.
Chip capacitors should be used for supply bypassing (see
Figure 15). One end should be connected to the ground plane
and the other within 1/8 in. of each power pin. An additional tan-
talum electrolytic capacitor (4.7 µF – 10 µF) should be connected
in parallel.
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance greater than 1.5 pF at the inverting input
will significantly affect high speed performance when operating
at low noninverting gains.
Stripline design techniques should be used for long signal traces
(greater than about 1 in.). These should be designed with the
proper system characteristic impedance and be properly
terminated at each end.
C1
0.01␮F
C2
0.01␮F
C4
10␮F
C3
10␮F
R
T
INVERTING CONFIGURATION
V
IN
V
OUT
+V
S
–V
S
R
G
R
F
R
O
C1
0.01␮F
C2
0.01␮F
C4
10␮F
C3
10␮F
R
T
NONINVERTING CONFIGURATION
V
IN
+V
S
–V
S
V
OUT
R
G
R
F
R
O
Figure 15. Inverting and Noninverting Configurations